SN74LV595ADBR Datasheets | Logic - Shift Registers Shift Shift Register Element Bit 16-SSOP
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SN74LV595ADBR, SN74LV595ADBR Datasheet,SN74LV595ADBR PDF,Texas Instruments
Descriptions
IC 8BIT SHIFT REG 3ST-OUT 16SSOP:Digi-Key
The LV595A devices are 8-bit shift registers designed for 2-V to 5.5-V VCC operation. These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR)\ input, serial (SER) input, and a serial output for cascading. When the output-enable (OE)\ input is high, all outputs except QH are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.:Texas Instruments