Bus XCVR Single 18-CH 3-ST 56-Pin TSSOP T/R:Avnet
IC UNIV BUS TXRX 18BIT 56TSSOP:Digi-Key
These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB\ and CLKBA\) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB\ is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the high-to-low transition of CLKAB\. Output enable OEAB\ is active low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, CLKBA\, and CLKENBA\. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16600 is characterized for operation over the full military temperature range of -55C to 125C. The SN74ABT16600 is characterized for operation from -40C to 85C:Texas Instruments