IC UNIV BUS TXRX 18BIT 56SSOP:Heisener Electronics
16 BIT REG TRANSCEIVER:Avnet
These 18-bit universal bus transceivers can be operated in transparent, latched, or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output-enable (OEAB and OEBA\), latch enable (LEAB and LEBA), and clock inputs (CLKAB\ and CLKBA\) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB\ is held at a HIGH or LOWlogic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOWtransition of CLKAB\. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA\, LEBA, and LKBA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16500T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162500T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162500T is ideal for driving transmission lines.:Texas Instruments