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Home  Logic - Buffers, Drivers, Receivers, Transceivers  74AHCT374PW Datasheets | Logic - Buffers, Drivers, Receivers, Transceivers Element Bit per Element Output

Jan 5 2021

74AHCT374PW Datasheets | Logic - Buffers, Drivers, Receivers, Transceivers Element Bit per Element Output

Product Overview

Image:
74AHCT374PW
Manufacturer Part#: 74AHCT374PW
Product Category: Logic - Buffers, Drivers, Receivers, Transceivers
Stock: No
Manufacturer: Nexperia USA Inc.
Description: Element Bit per Element Output
Datasheet: 74AHCT374PW Datasheet
Package: N/A
Minimum: 1
Lead Time: 0 Weeks
Quantity: On Order
Send RFQ: Inquiry

Reference Price

Qty Unit Price Ext. Price
2253: 0.11097 250.01541

CAD Models

Product Attributes

Alternative Models

Part Compare Manufacturers Category Description
Mfr.Part#:74AHCT374PW Compare: Current Part Manufacturers:Nexperia Category: Description: 74AHCT374PW
Mfr.Part#:74VHCT374AMTCX Compare: 74AHCT374PW VS 74VHCT374AMTCX Manufacturers:Fairchild Category:Flip Flops Description: Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1Element 20Pin TSSOP T/R
Mfr.Part#:74VHCT374AMTC Compare: 74AHCT374PW VS 74VHCT374AMTC Manufacturers:Fairchild Category:Flip Flops Description: Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1Element 20Pin TSSOP Rail
Mfr.Part#:74VHCT374AMTC Compare: 74AHCT374PW VS 74VHCT374AMTC Manufacturers:ON Semiconductor Category:Flip Flops Description: Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1Element 20Pin TSSOP Tube

Descriptions

There is no relevant information available for this part yet.

FEATURES

General description

The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input (CP) and an output enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D inputs that meet the set-up and hold times requirements for the LOW-to-HIGH CP transition.
When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

Features

■ Balanced propagation delays
■ All inputs have Schmitt-trigger actions
■ Inputs accept voltages higher than VCC
■ Common 3-state output enable input
■ Input levels:
◆ For 74AHC374: CMOS level
◆ For 74AHCT374: TTL level
■ ESD protection:
◆ HBM EIA/JESD22-A114E exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V
◆ CDM EIA/JESD22-C101C exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C

ECCN / UNSPSC

Description Value
USHTS: 8542310001
CNHTS: 8542319000
TARIC: 8542319000
ECCN: EAR99

Environmental & Export Classifications

There is no relevant information available for this part yet.

Documents & Media

Datasheets: 74AHCT374PW Datasheet

Distributors

Image PartNo Manufacturer Descriptions Stock Step Price
74AHCT374PW 74AHCT374PW Nexperia USA Inc. Element Bit per Element Output On Order

2,253:$$0.11097

74AHCT374PW 74AHCT374PW Nexperia Flip Flops OCTAL D 3-STATE On Order

N/A

74AHCT374PW 74AHCT374PW Nexperia Bus Driver, AHCT/VHCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20 On Order

$0.1120

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  • Product Attributes
  • Descriptions
  • Features
  • CAD Models

There is no relevant information available for this part yet.

FEATURES

General description

The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input (CP) and an output enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D inputs that meet the set-up and hold times requirements for the LOW-to-HIGH CP transition.
When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

Features

■ Balanced propagation delays
■ All inputs have Schmitt-trigger actions
■ Inputs accept voltages higher than VCC
■ Common 3-state output enable input
■ Input levels:
◆ For 74AHC374: CMOS level
◆ For 74AHCT374: TTL level
■ ESD protection:
◆ HBM EIA/JESD22-A114E exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V
◆ CDM EIA/JESD22-C101C exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C

There is no relevant information available for this part yet.