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Home  Logic - Buffers, Drivers, Receivers, Transceivers  74AHCT125BQ-Q100115 Datasheets | Logic - Buffers, Drivers, Receivers, Transceivers Element Bit per Element Output

Jan 5 2021

74AHCT125BQ-Q100115 Datasheets | Logic - Buffers, Drivers, Receivers, Transceivers Element Bit per Element Output

Product Overview

Image:
74AHCT125BQ-Q100115
Manufacturer Part#: 74AHCT125BQ-Q100115
Product Category: Logic - Buffers, Drivers, Receivers, Transceivers
Stock: No
Manufacturer: NXP USA Inc.
Description: Element Bit per Element Output
Datasheet: N/A
Package: N/A
Minimum: 1
Lead Time: 1 Weeks
Quantity: On Order
Send RFQ: Inquiry

Reference Price

Qty Unit Price Ext. Price
2102: 0.11898 250.09596

CAD Models

Symbol

74AHCT125BQ-Q100115  Symbol

Product Attributes

Descriptions

There is no relevant information available for this part yet.

FEATURES

General description

The 74AHC125; 74AHCT125 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A.
The 74AHC125; 74AHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state.
The 74AHC125; 74AHCT125 is identical to the 74AHC126; 74AHCT126 but has active LOW enable inputs.

Features

■ Balanced propagation delays
■ All inputs have a Schmitt-trigger action
■ Inputs accepts voltages higher than VCC
■ For 74AHC125 only: operates with CMOS input levels
■ For 74AHCT125 only: operates with TTL input levels
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101C exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C

Environmental & Export Classifications

Description Value
RoHS Status: Not applicable
Moisture Sensitivity Level (MSL): 3 (168 Hours)
REACH Status: Vendor Undefined
ECCN: EAR99
HTSUS: 8542.39.0001

Distributors

Image PartNo Manufacturer Descriptions Stock Step Price
74AHCT125BQ-Q100115 74AHCT125BQ-Q100115 NXP USA Inc. Element Bit per Element Output On Order

2,102:$$0.11898

74AHCT125BQ-Q100115 74AHCT125BQ-Q100115 NXP Semiconductors N/A On Order

1:$0.111

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  • Product Attributes
  • Descriptions
  • Features
  • CAD Models

There is no relevant information available for this part yet.

FEATURES

General description

The 74AHC125; 74AHCT125 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A.
The 74AHC125; 74AHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state.
The 74AHC125; 74AHCT125 is identical to the 74AHC126; 74AHCT126 but has active LOW enable inputs.

Features

■ Balanced propagation delays
■ All inputs have a Schmitt-trigger action
■ Inputs accepts voltages higher than VCC
■ For 74AHC125 only: operates with CMOS input levels
■ For 74AHCT125 only: operates with TTL input levels
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101C exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C

Symbol

74AHCT125BQ-Q100115  Symbol