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Home  Logic - Flip Flops  74ABT16823ADL,512 Datasheets | Logic - Flip Flops IC FF D-TYPE DUAL 9BIT 56SSOP

Oct 8 2020

74ABT16823ADL,512 Datasheets | Logic - Flip Flops IC FF D-TYPE DUAL 9BIT 56SSOP

Product Overview

Image:
74ABT16823ADL-512
Manufacturer Part#: 74ABT16823ADL,512
Product Category: Logic - Flip Flops
Stock: No
Manufacturer: NXP USA Inc.
Description: IC FF D-TYPE DUAL 9BIT 56SSOP
Datasheet: 74ABT16823A
Package: 56-SSOP
Minimum: 1
Lead Time: 3(168 Hours)
Quantity: On Order
Send RFQ: Inquiry

74ABT16823ADL,512 Images are for reference only.

74ABT16823ADL,512

CAD Models

Product Attributes

Manufacturer: NXP USA Inc.
Series: 74ABT
Packaging: Tube
Part Status: Obsolete
Function: Master Reset
Type: D-Type
Output Type: Tri-State Non-Inverted
Number of Elements: 2
Number of Bits per Element: 9
Clock Frequency: 190MHz
Max Propagation Delay @ V Max CL: 3.2ns @ 5V 50pF
Trigger Type: Positive Edge
Current - Output High Low: 32mA 64mA
Voltage - Supply: 4.5V ~ 5.5V
Current - Quiescent (Iq): 1mA
Input Capacitance: 4pF
Operating Temperature: -40°C ~ 85°C (TA)
Mounting Type: Surface Mount
Supplier Device Package: 56-SSOP
Package / Case: 56-BSSOP (0.295" 7.50mm Width)
Base Part Number: 74ABT16

Descriptions

There is no relevant information available for this part yet.

FEATURES

DESCRIPTION

The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity.

FEATURES

• Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
• Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors
• Live insertion/extraction permitted
• Power-up 3-State
• Power-up Reset
• Output capability: +64 mA/–32 mA
• Latch-up protection exceeds 500 mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

Environmental & Export Classifications

Description Value
RoHS Status: ROHS3 Compliant
Moisture Sensitivity Level (MSL): 1 (Unlimited)

Documents & Media

Datasheets: 74ABT16823A
PCN Obsolescence/ EOL: Multiple Devices 26/Dec/2012
HTML Datasheet: Multiple Devices Dec/2012

Distributors

Image PartNo Manufacturer Descriptions Stock Step Price
74ABT16823ADL-512 74ABT16823ADL,512 NXP USA Inc. IC FF D-TYPE DUAL 9BIT 56SSOP On Order

N/A

74ABT16823ADL-512 74ABT16823ADL,512 NXP Semiconductors 74ABT16823A - 18-bit bus interface D-type flip-flop with reset and enable (3-State) SSOP 56-Pin On Order

N/A

Popularity by Region

  • 1. United States
    100
  • 2. Philippines
    97
  • 3. China
    88
  • 4. Thailand
    84
  • 5. Spain
    84
  • 6. France
    84
  • 7. Kazakhstan
    84
  • 8. India
    83
  • 9. Hong Kong
    81
  • 10. Israel
    80
  • 11. Russia
    79
  • 12. Brazil
    79
  • 13. Taiwan
    78
  • 14. Tunisia
    78
  • 15. Japan
    77
  • 16. Poland
    77
  • 17. Mexico
    77
  • 18. Germany
    77
  • 19. Argentina
    73
  • 20. Italy
    70

74ABT16823ADL,512 Popularity by Region

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  • Product Attributes
  • Descriptions
  • Features
  • CAD Models
Manufacturer: NXP USA Inc.
Series: 74ABT
Packaging: Tube
Part Status: Obsolete
Function: Master Reset
Type: D-Type
Output Type: Tri-State Non-Inverted
Number of Elements: 2
Number of Bits per Element: 9
Clock Frequency: 190MHz
Max Propagation Delay @ V Max CL: 3.2ns @ 5V 50pF
Trigger Type: Positive Edge
Current - Output High Low: 32mA 64mA
Voltage - Supply: 4.5V ~ 5.5V
Current - Quiescent (Iq): 1mA
Input Capacitance: 4pF
Operating Temperature: -40°C ~ 85°C (TA)
Mounting Type: Surface Mount
Supplier Device Package: 56-SSOP
Package / Case: 56-BSSOP (0.295" 7.50mm Width)
Base Part Number: 74ABT16

There is no relevant information available for this part yet.

FEATURES

DESCRIPTION

The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity.

FEATURES

• Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
• Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors
• Live insertion/extraction permitted
• Power-up 3-State
• Power-up Reset
• Output capability: +64 mA/–32 mA
• Latch-up protection exceeds 500 mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

There is no relevant information available for this part yet.