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Jun 1 2020

MT41J256M16RE-15EIT:D Datasheets| MICRON| PDF| Price| In Stock

Product Overview

Kynix Part #:

KY32-MT41J256M16RE-15EIT:D

Manufacturer Part#:

MT41J256M16RE-15EIT:D

Product Category:

Memory

Stock:

Yes

Manufacturer:

MICRON

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Description:

-

Datasheet:

MT41J256M16RE-15EIT:D Datasheet

Package:

FBGA

Quantity:

2103 PCS


MT41J256M16RE-15EIT:D Images are for reference only.

 MT41J256M16RE-15EIT:D Image


CAD Models

There is no relevant information available for this part yet.


Product Attributes

Categories

Integrated Circuits (ICs)

Memory ICs

EU RoHS Compliant

Yes

REACH Compliant

Yes

Status

Obsolete

Package Description

10 X 14 MM, LEAD FREE, FBGA-96

Brand

MICRON

Sub Category

DRAMs

Access Mode

MULTI BANK PAGE BURST

Address Bus Width

18 b

Access Time-Max

0.255 ns

Base Part Number

MT41J256M4

Clock Frequency-Max (fCLK)

667 MHz

Chip Density (bit)

4G

Data Bus Width

16 b

DRAM Type

DDR3 SDRAM

I/O Type

COMMON

Interleaved Burst Length

8

JESD-30 Code

R-PBGA-B96

JESD-609 Code

e1

Memory Density

4294967296 bit

Memory IC Type

DDR DRAM

Memory Width

16

Memory Type

Volatile

Memory Format

DRAM

Memory Interface

Parallel

Number of Terminals

96

Number of Words

268435456 words

Number of Words Code

256000000

Number of Functions

1

Number of Ports

1

Number of Banks

8

Number of Bits per Word

16 b

Number of I/O Lines

16 b

Organization

256MX16

Operating Mode

SYNCHRONOUS

Operating Temperature

-40°C~85°C

Output Characteristics

3-STATE

Package Body Material

PLASTIC/EPOXY

Package Code

TFBGA

Package Equivalence Code

BGA96,9X16,32

Package Shape

RECTANGULAR

Package Style

GRID ARRAY, THIN PROFILE, FINE PITCH

Pbfree Code

Yes

Peak Reflow Temperature (Cel)

260

Power Supplies

1.5 V

Pin Count

96

PCB changed

96

Product Dimensions

14 x 10 x 0.75 mm

Package / Case

96-TFBGA

Supplier Device Package

96-FBGA (10x14)

Qualification Status

Not Qualified

Risk Rank

5.69

Refresh Cycles

8192

Rohs Code

Yes

Seated Height-Max

1.2 mm

Sequential Burst Length

8

Standby Current-Max

0.02 A

Supply Current-Max

0.285 mA

Supply Voltage-Nom (Vsup)

1.5 V

Supply Voltage-Min (Vsup)

1.425 V

Supply Voltage-Max (Vsup)

1.575 V

Surface Mount

Yes

Technology

CMOS

Type

DDR3 SDRAM

Temperature Grade

INDUSTRIAL

Terminal Finish

Tin/Silver/Copper (Sn/Ag/Cu)

Terminal Form

BALL

Terminal Pitch

0.8 mm

Terminal Position

BOTTOM

Time@Peak Reflow Temperature-Max (s)

30

Length

14.0 mm

Width

10.0 mm

Additional Feature

AUTO/SELF REFRESH


Features

VDD = VDDQ = 1.5V ±0.075V

1.5V center-terminated push/pull I/O

Differential bidirectional data strobe

8n-bit prefetch architecture

Differential clock inputs (CK, CK#)

8 internal banks

Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals

Programmable CAS READ latency (CL)

Posted CAS additive latency (AL)

Programmable CAS WRITE latency (CWL) based on tCK

Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])

Selectable BC4 or BL8 on-the-fly (OTF)

Self refresh mode

TC of 0°C to 95°C

      64ms, 8192 cycle refresh at 0°C to 85°C

      32ms, 8192 cycle refresh at 85°C to 95°C

Self refresh temperature (SRT)

Automatic self refresh temperature (ASR)

Write leveling

Multipurpose register

Output driver calibration


Advantages and Disadvantages

Advantages

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth b hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode.


Applications

There is no relevant information available for this part yet.


Product Functions

There is no relevant information available for this part yet.


ECCN / UNSPSC

Description

Value

ECCN

EAR99

HTSN

8542320036

SCHEDULE B

8542320023


Environmental & Export Classifications

Moisture Sensitivity Level (MSL)

3 (168 Hours)

Lead Free Status / RoHS Status

Lead free / RoHS Compliant


Documents & Media

There is no relevant information available for this part yet.


Product Manufacturer

Micron Technology, Inc. is an American producer of computer memory and computer data storage including dynamic random-access memory, flash memory, and USB flash drives. It is headquartered in Boise, Idaho. Its consumer products are marketed under the brands Crucial[3] and Ballistix. Micron and Intel together created IM Flash Technologies, which produces NAND flash memory.


Product Range

Memory

Storage

Advanced Solutions

DRAM

DRAM Modules

Graphics Memory

Managed NAND

Multichip Packages

NAND Flash

NOR Flash

Memory Cards

Solid State Drives

3D XPoint Technology

Advanced Computing Solutions

Authenta Security Solution

Heterogeneous-Memory Storage Engine


Distributors

Distributor

Stock

Manufacturer

Descriptions

Kynix

2103 PCS

Micron Technology

-

Digi-Key

1000 PCS

Micron Technology

IC DRAM 4G PARALLEL 96FBGA

Avnet

Non-stock

Micron Technology

DRAM Chip DDR3 SDRAM 4G-Bit 256Mx16 1.5V 96-Pin F-BGA

Arrow

Not Available

Micron Technology

DRAM Chip DDR3 SDRAM 4Gbit 256Mx16 1.5V 96-Pin FBGA


Alternative Models

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Popularity by Region

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Market Price Analysis

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