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Jun 3 2020

KMPC852TCZT100A Datasheets| NXP| PDF| Price| In Stock

Product Overview

Kynix Part #:

KY32-KMPC852TCZT100A

Manufacturer Part#:

KMPC852TCZT100A

Product Category:

IC Chips

Stock:

Yes

Manufacturer:

Freescale Semiconductor - NXP

Click Purchase button to buy original genuine KMPC852TCZT100A

Description:

IC MPU MPC8XX 100MHZ 256BGA

Datasheet:

KMPC852TCZT100A Datasheet

Package:

-

Quantity:

72 PCS

KMPC852TCZT100A Images are for reference only.

 


CAD Models

There is no relevant information available for this part yet.


Product Attributes

Additional Feature

ALSO REQUIRES 3.3V SUPPLY

Additional Interfaces

HDLC/SDLC, PCMCIA, SPI, UART

Address Bus Width

32

Bit Size

32

Boundary Scan

YES

Case/Package

BGA

Category

Integrated Circuits (ICs) > Embedded - Microprocessors

Clock Frequency-Max

66 MHz

Co-Processors/DSP

Communications; CPM

Core Processor

MPC8xx

Data Bus Width

32 b

Description

IC MPU MPC8XX 100MHZ 256BGA

Display & Interface Controllers

-

ECCN Code

5A991

Ethernet

10 Mbps (1)

External Data Bus Width

32

Format

FIXED POINT

Frequency

100 MHz

Graphics Acceleration

No

Halogen Free

Not Halogen Free

HTS Code

8542.31.00.01

Ihs Manufacturer

FREESCALE SEMICONDUCTOR

Integrated Cache

YES

JESD-30 Code

S-PBGA-B256

JESD-609 Code

e0

Lead Free

Contains Lead

Length

23mm

Low Power Mode

YES

Manufacturer

NXP Semiconductors / Freescale

Manufacturer Part Number

KMPC852TCZT100A

Max Frequency

100 MHz

Max Operating Temperature

100 °C

Min Operating Temperature

-40 °C

Moisture Sensitivity Level

3

Number of Cores

1

Number of Cores/Bus Width

1 Core, 32-Bit

Number of Pins

256

Number of Terminals

256

Operating Supply Voltage

1.8 V

Package Body Material

PLASTIC/EPOXY

Package Code

BGA

Part Life Cycle Code

Obsolete

Part Number

KMPC852TCZT100A

Peak Reflow Temperature (Cel)

220

Pin Count

256

Qualification Status

Not Qualified

RAM Controllers

DRAM

RAM Size

8 kB

Reach Compliance Code

not_compliant

Risk Rank

8.26

RoHS

Compliant

Rohs Code

No

SATA

-

Seated Height-Max

2.54 mm

Security Features

-

Series

MPC8xx

Speed

100MHz

Supply Voltage-Max

1.9 V

Supply Voltage-Min

1.7 V

Supply Voltage-Nom

1.8 V

Surface Mount

YES

Technology

CMOS

Terminal Finish

TIN LEAD

Terminal Form

BALL

Terminal Pitch

1.27 mm

Terminal Position

BOTTOM

Time@Peak Reflow Temperature-Max (s)

30

uPs/uCs/Peripheral ICs Type:

MICROPROCESSOR, RISC

USB

-

Voltage - I/O

3.3V

Weight

1.724048 g

Width

23 mm


Features

The MPC852T is comprised of three modules that each use a 32-bit internal bus: an MPC8xx core, system integration unit (SIU), and communication processor module (CPM). The following list summarizes the key MPC852T features:

  • Embedded MPC8xx core up to 100 MHz
  • Maximum frequency operation of the external bus is 66 MHz

— 50/66 MHz core frequencies support both 1:1 and 2:1 modes

— 80/100 MHz core frequencies support 2:1 mode only

  • Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit general-purpose registers (GPRs)

— The core performs branch prediction with conditional prefetch, without conditional execution.

— 4-Kbyte data cache and 4-Kbyte instruction cache

      • 4-Kbyte instruction caches is two-way, set-associative with 128 sets
      • 4-Kbyte data cachesis two-way, set-associative with 128 sets
      • Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks
      • Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis

— MMUs with 32-entry TLB, fully associative instruction, and data TLBs

— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces, and 16 protection groups

  • Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
  • 32 address lines
  • Memory controller (eight banks)

— Contains complete dynamic RAM (DRAM) controller

— Each bank can be a chip select or RAS to support a DRAM bank 

— Up to 30 wait states programmable per memory bank — Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices

— DRAM controller-programmable to support most size and speed memory interfaces

— Four CAS lines, four WE lines, and one OE line

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbytes–256 Mbytes)

— Selectable write protection

— On-chip bus arbitration logic

  • Fast Ethernet controller (FEC)
  • General-purpose timers

— Two 16-bit timers or one 32-bit timer

— Gate mode can enable or disable counting

— Interrupt can be masked on reference match and event capture

  • System integration unit (SIU)

— Bus monitor

— Software watchdog

— Periodic interrupt timer (PIT)

— Low-power stop mode

— Clock synthesizer

— Decrementer and time base

— Reset controller

— IEEE 1149.1™ standard test access port (JTAG)

  • Interrupts

— Seven external interrupt request (IRQ) lines

— Seven port pins with interrupt capability

— Eighteen internal interrupt sources

— Programmable priority between SCCs

— Programmable highest-priority request

  • Communications processor module (CPM)

— RISC controller

— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and RESTART TRANSMIT)

— Supports continuous mode transmission and reception on all serial channels

— 8-Kbytes of dual-port RAM

— Eight serial DMA (SDMA) channels

— Three parallel I/O registers with open-drain capability 

  • Two baud rate generators

— Independent (can be connected toany SCC3/4 or SMC1)

— Allows changes during operation

— Autobaud support option

  • Two SCCs (serial communication controllers)

 — Ethernet/IEEE 802.3® standard optional on SCC3 and SCC4, supporting full 10-Mbps operation

— HDLC/SDLC

— HDLC bus (implements an HDLC-based local area network (LAN))

— Universal asynchronous receiver transmitter (UART)

— Totally transparent (bit streams)

— Totally transparent (frame-based with optional cyclic redundancy check (CRC))

  • One SMC (serial management channel)

— UART

  • One SPI (serial peripheral interface)

— Supports master and slave modes

— Supports multimaster operation on the same bus

  • PCMCIA interface

— Master (socket) interface, release 2.1 compliant

— Supports one independent PCMCIA socket; 8-memory or I/O windows supported

  • Debug interface

— Eight comparators: four operate on instruction address, two operate on data address, and two operate on data

— Supports conditions: = ≠ < >

— Each watchpoint can generate a break point internally

  • Normal high and normal low power modes to conserve power
  • 8 V core and 3.3-V I/O operation with 5-V TTL compatibility. Refer to Table 5 for a listing of the 5-V tolerant pins.

Advantages and Disadvantages

Advantages

The MPC852T is a 0.18-micron derivative of the MPC860 PowerQUICC™ family, and can operate up to 100 MHz on the MPC8xx core with a 66-MHz external bus. The MPC852T has a 1.8-V core and a 3.3-V I/O operation with 5-V TTL compatibility. The MPC852T integrated communications controller is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in Ethernet control applications, including CPE equipment, Ethernet routers and hubs, VoIP clients, and WiFi access points. The MPC852T is a PowerPC architecture-based derivative of the MPC860 Quad Integrated Communications Controller (PowerQUICC). The CPU on the MPC852T is a MPC8xx core, a 32-bit microprocessor that implements the PowerPC architecture, incorporating memory management units (MMUs) and instruction and data caches. The MPC852T is the subset of this family of devices.


Applications

There is no relevant information available for this part yet.


Product Functions

There is no relevant information available for this part yet.


ECCN / UNSPSC

Description

Value

ECCN

3A991

HTSN

8542.31.00.01


Environmental & Export Classifications

Moisture Sensitivity Level (MSL)

3 (168 Hours)

Lead Free Status / RoHS Status

Lead free / RoHS non-compliant


Documents & Media

Datasheets

MPC852T

Design Resources

Development Tool Selector


Product Manufacturer

NXP Semiconductors N.V. is a Dutch global semiconductor manufacturer headquartered in Eindhoven, Netherlands. The company employs approximately 31,000 people in more than 35 countries, including 11,200 engineers in 33 countries. NXP reported revenue of $6.1 billion in 2015, including one month of revenue contribution from recently merged Freescale Semiconductor.

On October 27, 2016, it was announced that Qualcomm would try to buy NXP, but because the Chinese merger authority did not approve the acquisition before the deadline set by Qualcomm, it was effectively canceled on 26 July 2018.


Product Range

Devices

Boards

Developer Tools

ACAPs

Accelerator Cards

Vivado Design Suite - HLx Editions

FPGAs & 3D ICs

Evaluation Boards

SDAccel Development Environment

SoCs, MPSoCs & RFSoCs

System-on-Modules (SoMs)

SDSoC Development Environment


Distributors

Distributor

Stock

Manufacturer

Descriptions

Kynix

72 PCS

NXP Semiconductors

IC MPU MPC8XX 100MHZ 256BGA

Quest Components  

8 PCS

Freescale Semiconductor

-


Alternative Models

Manufacturer

Manufacturer Part No.

Lifecycle Status Indicator

NXP Freescale

MPC852TCZT100A

Volume Production

NXP Freescale

MPC852TCVR100A

Volume Production


Popularity by Region


KMPC852TCZT100A Popularity by Region


Market Price Analysis

There is no relevant information available for this part yet.


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