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May 29 2020

KMPC8349EZUAJDB Datasheets| NXP| PDF| Price| In Stock

Product Overview

Kynix Part #:

KY32-KMPC8349EZUAJDB

Manufacturer Part#:

KMPC8349EZUAJDB

Product Category:

Embedded - Microprocessors

Stock:

Yes

Manufacturer:

Freescale Semiconductor - NXP

Click Purchase button to buy original genuine KMPC8349EZUAJDB

Description:

IC MPU MPC83XX 533MHZ 672TBGA

Datasheet:

KMPC8349EZUAJDB Datasheet

Package:

672-LBGA

Quantity:

82 PCS

KMPC8349EZUAJDB Images are for reference only.

 


CAD Models

KMPC8349EZUAJDB Footprint


Product Attributes

Additional Interfaces

DUART, I²C, PCI, SPI

Alternative Part (Replacement Part)

KMPC8349EZUAJDB

Applications

E-mail for more information

Base Part Number

KMPC83

Category

Integrated Circuits (ICs)

Co-Processors/DSP

Security; SEC

Core Processor

PowerPC e300

Data Bus Width

32b

Display & Interface Controllers

-

Ethernet

10/100/1000Mbps (2)

Family

Embedded - Microprocessors

Frequency

533MHz

Graphics Acceleration

No

Halogen Free

Halogen Free

Manufacturer

Freescale Semiconductor - NXP

Max Frequency

533MHz

Max Operating Temperature

105°C

Min Operating Temperature

0°C

Number of Cores

1

Number of Cores/Bus Width

1 Core, 32-Bit

Number of Pins

672

Operating Supply Voltage

1.2V

Operating Temperature

0°C ~ 105°C (TA)

Package / Case

672-LBGA

Package Quantity

2

Packaging

Tray 

Part Status

Obsolete

Radiation Hardening

No

Radiation Hardening

No

RAM Controllers

DDR, DDR2

RoHS

Compliant

SATA

-

SATA

-

Security Features

Cryptography, Random Number Generator

Series

MPC83xx

Speed

533MHz

Supplier Device Package

672-TBGA (35x35)

USB

USB 2.0 + PHY (2)

Voltage - I/O

1.8V, 2.5V, 3.3V

Weight

0.327455oz


Features

  • Embedded PowerPC e300 processor core; operates at up to 667 MHz

— High-performance, superscalar processor core

— Floating-point, integer, load/store, system register, and branch processing units

— 32-Kbyte instruction cache, 32-Kbyte data cache

— Lockable portion of L1 cache

— Dynamic power management

— Software-compatible with the other Freescale processor families that implement Power Architecture technology

 

  • Double data rate, DDR1/DDR2 SDRAM memory controller

— Programmable timing supporting DDR1 and DDR2 SDRAM

— 32- or 64-bit data interface, up to 400 MHz data rate

— Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable

— DRAM chip configurations from 64 Mbits to 1 Gbit with ×8/×16 data ports

— Full error checking and correction (ECC) support

— Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)

— Contiguous or discontiguous memory mapping

— Read-modify-write support

— Sleep-mode support for SDRAM self refresh

— Auto refresh

— On-the-fly power management using CKE

— Registered DIMM support

— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2

 

  • Dual three-speed (10/100/1000) Ethernet controllers (TSECs)

— Dual controllers designed to comply with IEEE 802.3™, 802.3u™, 820.3x™, 802.3z™, 802.3ac™ standards

— Ethernet physical interfaces:

– 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex

– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex

— Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100

programming models

— 9.6-Kbyte jumbo frame support

— RMON statistics support

— Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module

— MII management interface for control and status

— Programmable CRC generation and checking

 

  • Dual PCI interfaces

— Designed to comply with PCI Specification Revision 2.3

— Data bus width options:

– Dual 32-bit data PCI interfaces operating at up to 66 MHz

– Single 64-bit data PCI interface operating at up to 66 MHz

— PCI 3.3-V compatible

— PCI host bridge capabilities on both interfaces

— PCI agent mode on PCI1 interface

— PCI-to-memory and memory-to-PCI streaming

— Memory prefetching of PCI read accesses and support for delayed read transactions

— Posting of processor-to-PCI and PCI-to-memory writes

— On-chip arbitration supporting five masters on PCI1, three masters on PCI2

— Accesses to all PCI address spaces

— Parity supported

— Selectable hardware-enforced coherency

— Address translation units for address mapping between host and peripheral

— Dual address cycle for target

— Internal configuration registers accessible from PCI

 

  • Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains fourcrypto-channels, a controller, and a set of crypto execution units (EUs):

— Public key execution unit (PKEU) :

– RSA and Diffie-Hellman algorithms

– Programmable field size up to 2048 bits

– Elliptic curve cryptography

– F2m and F(p) modes

– Programmable field size up to 511 bits

— Data encryption standard (DES) execution unit (DEU)

– DES and 3DES algorithms

– Two key (K1, K2) or three key (K1, K2, K3) for 3DES

– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

– Implements the Rijndael symmetric-key cipher

– Key lengths of 128, 192, and 256 bits

– ECB, CBC, CCM, and counter (CTR) modes

— XOR parity generation accelerator for RAID applications

— ARC four execution unit (AFEU)

– Stream cipher compatible with the RC4 algorithm

– 40- to 128-bit programmable key

— Message digest execution unit (MDEU)

– SHA with 160-, 224-, or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— Random number generator (RNG)

— Four crypto-channels, each supporting multi-command descriptor chains

– Static and/or dynamic assignment of crypto-execution units through an integrated controller

– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

 

  • Universal serial bus (USB) dual role controller

— USB on-the-go mode with both device and host functionality

— Complies with USB specification Rev. 2.0

— Can operate as a stand-alone USB device

– One upstream facing port

– Six programmable USB endpoints

— Can operate as a stand-alone USB host controller

– USB root hub with one downstream-facing port

– Enhanced host controller interface (EHCI) compatible

– High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

— External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)

 

  • Universal serial bus (USB) multi-port host controller

— Can operate as a stand-alone USB host controller

– USB root hub with one or two downstream-facing ports

– Enhanced host controller interface (EHCI) compatible

– Complies with USB Specification Rev. 2.0

— High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

— Direct connection to a high-speed device without an external hub

— External PHY with serial and low-pin count (ULPI) interfaces

 

  • Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 133 MHz

— Eight chip selects for eight external slaves

— Up to eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller

— Three protocol engines on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user-programmable machines (UPMs)

– Dedicated single data rate SDRAM controller

— Parity support

— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)

 

  • Programmable interrupt controller (PIC)

— Functional and programming compatibility with the MPC8260 interrupt controller

— Support for 8 external and 35 internal discrete interrupt sources

— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources

— Programmable highest priority request

— Four groups of interrupts with programmable priority

— External and internal interrupts directed to host processor

— Redirects interrupts to external INTA pin in core disable mode.

— Unique vector number for each interrupt source

 

  • Dual industry-standard I2C interfaces

— Two-wire interface

— Multiple master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

— System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware

 

  • DMA controller

— Four independent virtual channels

— Concurrent execution across multiple channels with programmable bandwidth control

— Handshaking (external control) signals for all channels: DMA_DREQ[0:3], DMA_DACK[0:3], DMA_DDONE[0:3]

— All channels accessible to local core and remote PCI masters

— Misaligned transfer capability

— Data chaining and direct mode

— Interrupt on completed segment and chain

 

  • DUART

— Two 4-wire interfaces (RxD, TxD, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

 

  • Serial peripheral interface (SPI) for master or slave
  • General-purpose parallel I/O (GPIO)

— 64 parallel I/O pins multiplexed on various chip interfaces

 

  • System timers

— Periodic interrupt timer

— Real-time clock

— Software watchdog timer

— Eight general-purpose timers

 

  • Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan
  • Integrated PCI bus and SDRAM clock generation

Advantages and Disadvantages

There is no relevant information available for this part yet.


Applications

There is no relevant information available for this part yet.


Product Functions

There is no relevant information available for this part yet.


ECCN / UNSPSC

There is no relevant information available for this part yet.


Environmental & Export Classifications

Moisture Sensitivity Level (MSL)

3 (168 Hours)

Lead Free Status / RoHS Status

Lead free / RoHS non-compliant


Documents & Media

Datasheets

MPC8349EA

Design Resources

Development Tool Selector

HTML Datasheet

MPC8349EA


Product Manufacturer

NXP Semiconductors N.V. is a Dutch global semiconductor manufacturer headquartered in Eindhoven, Netherlands. The company employs approximately 31,000 people in more than 35 countries, including 11,200 engineers in 33 countries. NXP reported revenue of $6.1 billion in 2015, including one month of revenue contribution from recently merged Freescale Semiconductor.

On October 27, 2016, it was announced that Qualcomm would try to buy NXP, but because the Chinese merger authority did not approve the acquisition before the deadline set by Qualcomm, it was effectively canceled on 26 July 2018.


Product Range

Devices

Boards

Developer Tools

ACAPs

Accelerator Cards

Vivado Design Suite - HLx Editions

FPGAs & 3D ICs

Evaluation Boards

SDAccel Development Environment

SoCs, MPSoCs & RFSoCs

System-on-Modules (SoMs)

SDSoC Development Environment


Distributors

Distributor

Stock

Manufacturer

Descriptions

Kynix

82 PCS

NXP Semiconductors

IC MPU MPC83XX 533MHZ 672TBGA

Zeano International Pte.ltd

10000 PCS

NXP Semiconductors

IC MPU MPC83XX 533MHZ 672TBGA  

Hxd Electronics Co.

621853 PCS

-

-  

Depu Electronics Co., Ltd

25500 PCS

NXP

NXP-2017  


Alternative Models

Manufacturer

Manufacturer Part No.

Lifecycle Status Indicator

NXP Freescale

MPC8349EZUAJDB

Volume Production


Popularity by Region

There is no relevant information available for this part yet.


Market Price Analysis

There is no relevant information available for this part yet.


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