Product Overview
| Image: |
 |
| Manufacturer Part#: | ADSP-BF561SKBCZ-5A |
| Product Category: | Embedded - DSP (Digital Signal Processors) |
| Stock: | No |
| Manufacturer: | Analog devices inc. |
| Description: | IC DSP CTLR 32BIT BKFN 256CSBGA |
| Datasheet: | ADSP-BF561 |
| Package: | 256-BGA, CSPBGA |
| Minimum: | 1 |
| Lead Time: | 3(168 Hours) |
| Quantity: | On Order |
| Send RFQ: | Inquiry |
Reference Price
| Qty | Unit Price | Ext. Price |
| 24: | 823.64000 | 19767.36000 |
ADSP-BF561SKBCZ-5A Images are for reference only.
CAD Models
Product Attributes
| Manufacturer: | Analog devices inc． |
| Series: | Blackfin® |
| Packaging: | Tray |
| Part status: | AcN/Ave |
| Type: | Fixed point |
| Interface: | Spi ssp uart |
| Clock rate: | 533mhz |
| Non-volaN/Ale memory: | External |
| On-chip ram: | 328kb |
| Voltage - i/o: | 2．50v 3．30v |
| Voltage - core: | 1．25v |
| OperaN/Ang temperature: | 0°c ~ 70°c (ta) |
| MounN/Ang type: | Surface mount |
| Package / case: | 256-bga cspbga |
| Supplier device package: | 256-cspbga (17x17) |
| Base part number: | Adsp-bf561 |
Descriptions
dsp fixed-point 16-bit 500mhz 500mips 256-pin csp-bga:netroflash
dsp, fixed, 16/32bit, 500mhz, cspbga-256; dsp type:fixed point; no. of bits:16 / 32bit; frequency:500mhz; flash memory size:-; dsp case style:cspbga; no. of pins:256pins; no. of i/o s:48i/o s; no. of mips:-; msl:msl 3 - 168 hours rohs compliant: yes:newark
the blackfin® processor family expands the performance envelope with the adsp-bf561. with two high performance blackfin processor cores, flexible cache architecture, enhanced dma subsystem, and dynamic power management (dpm) funcN/Aonality, the adsp-bf561 can support complex control and signal processing tasks while maintaining extremely high data throughput. the adsp-bf561 is a funcN/Aonal extension of the popular blackfin processor family and is ideally suited for a broad range of industrial, instrumentaN/Aon, medical, and consumer appliance applicaN/Aons—allowing for scalability based upon the required data bandwidth and mix of control, plus signal processing needed in the end product. high-level of integraN/Aon 328 kbytes of on-chip memory configured as: 32 kbytes of l1 instrucN/Aon memory sram/cache per core 64 kbytes of l1 data memory sram/cache per core 4 kbytes of l1 scratchpad memory per core 128 kbytes of low-latency shared l2 memory 32-bit memory controller providing glueless connecN/Aon to mulN/Aple banks of sdram, sram, flash or rom. two parallel peripheral interfaces units supporN/Ang itu-r 656 video data formats. two dual-channel, full-duplex, synchronous serial ports supporN/Ang eight stereo i2s channels. dual 16 channel dma controllers, supporN/Ang one and two-dimension transfers. spi-compaN/Able port. uart with support for irda®. 12 N/Amer/counters supporN/Ang pwm, pulsewidth and event count modes. 48 programmable flags/general purpose i/o. event handler. dual watchdog N/Amers. pll capable of 1x to 63x frequency mulN/AplicaN/Aon. 256-ball mini-bga and 297-ball sparse pbga packages.:analog devices
dsp, fixed, 16/32bit, 500mhz, cspbga-256; dsp type:fixed point; no. of bits:16 / 32bit; frequency:500mhz; flash memory size:-; dsp case style:cspbga; no. of pins:256pins; no. of i/o s:48i/o s; no. of mips:-; msl:msl 3 - 168 hours rohs compliant: yes:newark
the blackfin® processor family expands the performance envelope with the adsp-bf561. with two high performance blackfin processor cores, flexible cache architecture, enhanced dma subsystem, and dynamic power management (dpm) funcN/Aonality, the adsp-bf561 can support complex control and signal processing tasks while maintaining extremely high data throughput. the adsp-bf561 is a funcN/Aonal extension of the popular blackfin processor family and is ideally suited for a broad range of industrial, instrumentaN/Aon, medical, and consumer appliance applicaN/Aons—allowing for scalability based upon the required data bandwidth and mix of control, plus signal processing needed in the end product. high-level of integraN/Aon 328 kbytes of on-chip memory configured as: 32 kbytes of l1 instrucN/Aon memory sram/cache per core 64 kbytes of l1 data memory sram/cache per core 4 kbytes of l1 scratchpad memory per core 128 kbytes of low-latency shared l2 memory 32-bit memory controller providing glueless connecN/Aon to mulN/Aple banks of sdram, sram, flash or rom. two parallel peripheral interfaces units supporN/Ang itu-r 656 video data formats. two dual-channel, full-duplex, synchronous serial ports supporN/Ang eight stereo i2s channels. dual 16 channel dma controllers, supporN/Ang one and two-dimension transfers. spi-compaN/Able port. uart with support for irda®. 12 N/Amer/counters supporN/Ang pwm, pulsewidth and event count modes. 48 programmable flags/general purpose i/o. event handler. dual watchdog N/Amers. pll capable of 1x to 63x frequency mulN/AplicaN/Aon. 256-ball mini-bga and 297-ball sparse pbga packages.:analog devices
ECCN / UNSPSC
| Description | Value |
| Ushts: | 8542310001 |
| Cnhts: | 8542319000 |
| Mxhts: | 85423102 |
| Taric: | 8542319000 |
| Eccn: | 3a991.a.2 |
Environmental & Export Classifications
| Description | Value |
| Rohs status: | Rohs3 compliant |
| Moisture sensiN/Avity level (msl): | 3 (168 hours) |
Documents & Media
| Datasheets: | ADSP-BF561 |
| Design Resources: | Blackfin Processor Family |
| Featured Product: | Development Tool Selector |
| HTML Datasheet: | Analog Devices IoT and the Intelligence of Things |
| EDA / CAD Models: | Sensor Signal Chain |
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86. Macao34
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- Embedded - DSP (Digital Signal Processors),
- Embedded - DSP (Digital Signal Processors),BLACKFIN DSP PROCESSOR
- Embedded - DSP (Digital Signal Processors),IC FLOATING POINT DSP 256-BGA
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- Product Attributes
- Descriptions
- Features
- CAD Models
ADSP-BF561SKBCZ-5A Popularity by Region
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Ic dsp ctlr 32bit bkfn 256csbga
| Manufacturer: | Analog Devices Inc． |
| Series: | Blackfin® |
| Packaging: | Tray |
| Part Status: | Active |
| Type: | Fixed Point |
| Interface: | SPI SSP UART |
| Clock Rate: | 533MHz |
| Non-Volatile Memory: | External |
| On-Chip RAM: | 328kB |
| Voltage - I/O: | 2．50V 3．30V |
| Voltage - Core: | 1．25V |
| Operating Temperature: | 0°C ~ 70°C (TA) |
| Mounting Type: | Surface Mount |
| Package / Case: | 256-BGA CSPBGA |
| Supplier Device Package: | 256-CSPBGA (17x17) |
| Base Part Number: | ADSP-BF561 |
dsp fixed-point 16-bit 500mhz 500mips 256-pin csp-bga:netroflash
dsp, fixed, 16/32bit, 500mhz, cspbga-256; dsp type:fixed point; no. of bits:16 / 32bit; frequency:500mhz; flash memory size:-; dsp case style:cspbga; no. of pins:256pins; no. of i/o s:48i/o s; no. of mips:-; msl:msl 3 - 168 hours rohs compliant: yes:newark
the blackfin® processor family expands the performance envelope with the adsp-bf561. with two high performance blackfin processor cores, flexible cache architecture, enhanced dma subsystem, and dynamic power management (dpm) funcN/Aonality, the adsp-bf561 can support complex control and signal processing tasks while maintaining extremely high data throughput. the adsp-bf561 is a funcN/Aonal extension of the popular blackfin processor family and is ideally suited for a broad range of industrial, instrumentaN/Aon, medical, and consumer appliance applicaN/Aons—allowing for scalability based upon the required data bandwidth and mix of control, plus signal processing needed in the end product. high-level of integraN/Aon 328 kbytes of on-chip memory configured as: 32 kbytes of l1 instrucN/Aon memory sram/cache per core 64 kbytes of l1 data memory sram/cache per core 4 kbytes of l1 scratchpad memory per core 128 kbytes of low-latency shared l2 memory 32-bit memory controller providing glueless connecN/Aon to mulN/Aple banks of sdram, sram, flash or rom. two parallel peripheral interfaces units supporN/Ang itu-r 656 video data formats. two dual-channel, full-duplex, synchronous serial ports supporN/Ang eight stereo i2s channels. dual 16 channel dma controllers, supporN/Ang one and two-dimension transfers. spi-compaN/Able port. uart with support for irda®. 12 N/Amer/counters supporN/Ang pwm, pulsewidth and event count modes. 48 programmable flags/general purpose i/o. event handler. dual watchdog N/Amers. pll capable of 1x to 63x frequency mulN/AplicaN/Aon. 256-ball mini-bga and 297-ball sparse pbga packages.:analog devices
dsp, fixed, 16/32bit, 500mhz, cspbga-256; dsp type:fixed point; no. of bits:16 / 32bit; frequency:500mhz; flash memory size:-; dsp case style:cspbga; no. of pins:256pins; no. of i/o s:48i/o s; no. of mips:-; msl:msl 3 - 168 hours rohs compliant: yes:newark
the blackfin® processor family expands the performance envelope with the adsp-bf561. with two high performance blackfin processor cores, flexible cache architecture, enhanced dma subsystem, and dynamic power management (dpm) funcN/Aonality, the adsp-bf561 can support complex control and signal processing tasks while maintaining extremely high data throughput. the adsp-bf561 is a funcN/Aonal extension of the popular blackfin processor family and is ideally suited for a broad range of industrial, instrumentaN/Aon, medical, and consumer appliance applicaN/Aons—allowing for scalability based upon the required data bandwidth and mix of control, plus signal processing needed in the end product. high-level of integraN/Aon 328 kbytes of on-chip memory configured as: 32 kbytes of l1 instrucN/Aon memory sram/cache per core 64 kbytes of l1 data memory sram/cache per core 4 kbytes of l1 scratchpad memory per core 128 kbytes of low-latency shared l2 memory 32-bit memory controller providing glueless connecN/Aon to mulN/Aple banks of sdram, sram, flash or rom. two parallel peripheral interfaces units supporN/Ang itu-r 656 video data formats. two dual-channel, full-duplex, synchronous serial ports supporN/Ang eight stereo i2s channels. dual 16 channel dma controllers, supporN/Ang one and two-dimension transfers. spi-compaN/Able port. uart with support for irda®. 12 N/Amer/counters supporN/Ang pwm, pulsewidth and event count modes. 48 programmable flags/general purpose i/o. event handler. dual watchdog N/Amers. pll capable of 1x to 63x frequency mulN/AplicaN/Aon. 256-ball mini-bga and 297-ball sparse pbga packages.:analog devices
There is no relevant information available for this part yet.
There is no relevant information available for this part yet.