Product Overview
Image: |
![]() |
Manufacturer Part#: | ADSP-21262SKBCZ200 |
Product Category: | Embedded - DSP (Digital Signal Processors) |
Stock: | Yes |
Manufacturer: | Analog Devices Inc. |
Description: | IC DSP CTLR 32BIT 136CSBGA |
Datasheet: | ADSP-21261/62/66 |
Package: | 136-LFBGA, CSPBGA |
Minimum: | 1 |
Lead Time: | 3(168 Hours) |
Quantity: | 180 PCS |
Send RFQ: | Inquiry |
Reference Price
Qty | Unit Price | Ext. Price |
1: | 33.70000 | 33.70000 |
10: | 31.07900 | 310.79000 |
25: | 29.68200 | 742.05000 |
100: | 26.53920 | 2653.92000 |
ADSP-21262SKBCZ200 Images are for reference only.
Product Attributes
Manufacturer: | Analog Devices Inc. |
Series: | SHARC® |
Packaging: | Tray |
Part Status: | Active |
Type: | Floating Point |
Interface: | DAI SPI |
Clock Rate: | 200MHz |
Non-Volatile Memory: | ROM (512kB) |
On-Chip RAM: | 256kB |
Voltage - I/O: | 3.30V |
Voltage - Core: | 1.20V |
Operating Temperature: | 0°C ~ 70°C (TA) |
Mounting Type: | Surface Mount |
Package / Case: | 136-LFBGA CSPBGA |
Supplier Device Package: | 136-CSPBGA (12x12) |
Base Part Number: | ADSP-21262 |
Alternative Models
![]() |
priceUSD 34.274 |
Max Supply Voltage3.47 V |
Min Supply Voltage1.14 V |
Max Frequency333 MHz |
RAM Size384 kB |
Memory Size512 kB |
Memory TypeROM |
InterfaceDAI, SPI |
Data Bus Width32 b |
Number of Pins136 |
Case/PackageBGA |
Authorized Distributors4 |
![]() |
priceUSD 28.560 |
Max Supply Voltage3.47 V |
Min Supply Voltage1.14 V |
Max Frequency333 MHz |
RAM Size384 kB |
Memory Size512 kB |
Memory TypeROM, SRAM |
InterfaceDAI, SPI |
Data Bus Width32 b |
Number of Pins136 |
Case/PackageBGA |
Authorized Distributors6 |
![]() |
priceUSD 41.210 |
Max Supply Voltage3.47 V |
Min Supply Voltage1.14 V |
Max Frequency333 MHz |
RAM Size384 kB |
Memory Size512 kB |
Memory TypeROM |
InterfaceDAI, SPI |
Data Bus Width32 b |
Number of Pins136 |
Case/PackageBGA |
Authorized Distributors5 |
![]() |
priceUSD 20.704 |
Max Supply Voltage3.465 V |
Min Supply Voltage3.135 V |
Max Frequency150 MHz |
RAM Size68 kB |
Memory Size512 kB |
Memory TypeFLASH |
InterfaceCAN, EBI/EMI, I2C, SCI, SPI, UART, USART |
Data Bus Width32 b |
Number of Pins176 |
Case/PackageBGA |
Authorized Distributors4 |
![]() |
priceUSD 20.288 |
Max Supply Voltage3.47 V |
Min Supply Voltage1.14 V |
Max Frequency225 MHz |
RAM Size256 kB |
Memory Size384 kB |
Memory TypeFLASH, RAM, ROM, SDR, SDRAM |
InterfaceEBI/EMI, Ethernet, I2C, McASP, SPI, UART |
Data Bus Width32 b |
Number of Pins144 |
Case/PackageBGA |
Authorized Distributors10 |
Descriptions
Float-Pt Digital Signal Processor -Dsp, 32 Bit, 200Mhz, Bga-136:Newark
DSP Floating-Point 32-Bit 200MHz 200MIPS 136-Pin CSP-BGA:Avnet
The ADSP-21262 is the first member of the third-generation of SHARC® programmable DSPs. A range of applications such as high-quality audio and automotive entertainment systems, voice recognition, medical appliances and measurement devices benefit from the ADSP-21262’s integration of large on-chip memory with a wide variety of peripherals—thereby speeding time to market and keeping costs low. The ADSP-21262 is based on the SHARC DSP core that supports execution of 32-bit fixed-point and 32/40-bit floating-point arithmetic formats. With its core running at 200MHz (5 ns instruction cycle time), the ADSP-21262 is capable of executing complex Fast Fourier Transform (FFT) operations—1024-point complex FFT in 46us, more than 2.6x faster than comparatively priced processors. In audio applications, the single-instruction, multiple data (SIMD) mode effectively doubles the processor performance. The ADSP-21262 is designed with the highest level of integration, including 2 Mbit of on-chip dual-ported SRAM and 4 Mbit of mask programmable ROM memory. This large on-chip dual-ported memory enables sustained processor and I/O performance, without the need for external memory. System I/O is achieved through six full-duplex serial ports, four timers, a 16-bit parallel port, a serial peripheral interface (SPI), 22 zero-overhead Direct Memory Access (DMA) channels delivering fast data transfers without processor intervention and an innovative Digital Applications Interface (DAI) offering complete software control through its Signal Routing Unit (SRU). Digital Applications Interface (DAI) for Simplified I/O System Development The ADSP-21262 introduces the Digital Applications Interface (DAI), an architecture that enables complete software programmability of various peripherals. The flexibility and ease-of-use of the SHARC programming model, combined with the DAI, allow manufacturers to deploy one hardware configuration into multiple product offerings with different I/O requirements. Connections are made using the flexible Signal Routing Unit (SRU), a matrix routing group of pins that provides configurable and flexible connectivity between all DAI components and the SRU. The peripherals connected through the DAI are: a precision clock generator (PCG), an input data port (IDP), six SPORTS (serial ports), six flag inputs, six flag outputs, three timers and the SRU. The IDP provides an additional input path to the DSP core, configurable as 8 channels of receive serial data or as 7 channels of receive serial data and a single channel of up to a 20-bit wide parallel data. This level of integration enables the designer to take full advantage of a wide variety of peripherals without sacrificing the overall system performance. CROSSCORE Development Tools 3rd Generation SHARC DSP members are supported by ADI’s CROSSCORE brand of award winning development tools. The CROSSCORE components include the VisualDSP++™ software development environment, EZ-KIT Lite™ evaluation systems, and emulators. VisualDSP++ is an integrated software development environment, allowing for fast and easy development, debug, and deployment. The EZ-KIT Lite evaluation system provides an easy way to investigate the power of the ADI family of DSPs and begin to develop applications. Emulators are available for PCI and USB host platforms for rapid on-chip debugging. Additional development tools and algorithms are available from an extensive third-party development community.:Analog Devices
DSP Floating-Point 32-Bit 200MHz 200MIPS 136-Pin CSP-BGA:Avnet
The ADSP-21262 is the first member of the third-generation of SHARC® programmable DSPs. A range of applications such as high-quality audio and automotive entertainment systems, voice recognition, medical appliances and measurement devices benefit from the ADSP-21262’s integration of large on-chip memory with a wide variety of peripherals—thereby speeding time to market and keeping costs low. The ADSP-21262 is based on the SHARC DSP core that supports execution of 32-bit fixed-point and 32/40-bit floating-point arithmetic formats. With its core running at 200MHz (5 ns instruction cycle time), the ADSP-21262 is capable of executing complex Fast Fourier Transform (FFT) operations—1024-point complex FFT in 46us, more than 2.6x faster than comparatively priced processors. In audio applications, the single-instruction, multiple data (SIMD) mode effectively doubles the processor performance. The ADSP-21262 is designed with the highest level of integration, including 2 Mbit of on-chip dual-ported SRAM and 4 Mbit of mask programmable ROM memory. This large on-chip dual-ported memory enables sustained processor and I/O performance, without the need for external memory. System I/O is achieved through six full-duplex serial ports, four timers, a 16-bit parallel port, a serial peripheral interface (SPI), 22 zero-overhead Direct Memory Access (DMA) channels delivering fast data transfers without processor intervention and an innovative Digital Applications Interface (DAI) offering complete software control through its Signal Routing Unit (SRU). Digital Applications Interface (DAI) for Simplified I/O System Development The ADSP-21262 introduces the Digital Applications Interface (DAI), an architecture that enables complete software programmability of various peripherals. The flexibility and ease-of-use of the SHARC programming model, combined with the DAI, allow manufacturers to deploy one hardware configuration into multiple product offerings with different I/O requirements. Connections are made using the flexible Signal Routing Unit (SRU), a matrix routing group of pins that provides configurable and flexible connectivity between all DAI components and the SRU. The peripherals connected through the DAI are: a precision clock generator (PCG), an input data port (IDP), six SPORTS (serial ports), six flag inputs, six flag outputs, three timers and the SRU. The IDP provides an additional input path to the DSP core, configurable as 8 channels of receive serial data or as 7 channels of receive serial data and a single channel of up to a 20-bit wide parallel data. This level of integration enables the designer to take full advantage of a wide variety of peripherals without sacrificing the overall system performance. CROSSCORE Development Tools 3rd Generation SHARC DSP members are supported by ADI’s CROSSCORE brand of award winning development tools. The CROSSCORE components include the VisualDSP++™ software development environment, EZ-KIT Lite™ evaluation systems, and emulators. VisualDSP++ is an integrated software development environment, allowing for fast and easy development, debug, and deployment. The EZ-KIT Lite evaluation system provides an easy way to investigate the power of the ADI family of DSPs and begin to develop applications. Emulators are available for PCI and USB host platforms for rapid on-chip debugging. Additional development tools and algorithms are available from an extensive third-party development community.:Analog Devices
GENERAL DESCRIPTION
The ADSP-21261/ADSP-21262/ADSP-21266 SHARC® DSPs are members of the SIMD SHARC family of DSPs featuring Analog Devices, Inc., Super Harvard Architecture. The ADSP-2126x is source code compatible with the ADSP-21160 and ADSP-21161 DSPs as well as with first generation ADSP- 2106x SHARC processors in SISD (single-instruction, single data) mode. Like other SHARC DSPs, the ADSP-2126x are 32-bit/40-bit floating-point processors optimized for high performance audio applications with dual-ported on-chip SRAM, mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital application interface.SUMMARY
High performance 32-bit/40-bit floating-point processor optimized for high performance audio processingCode compatibility—at assembly level, uses the same instruction set as other SHARC DSPs
Processes high performance audio while enabling low system costs
Audio decoders and postprocessor algorithms support nonvolatile memory that can be configured to contain a combination of PCM 96 kHz, Dolby Digital, Dolby Digital Surround EX, DTS-ES Discrete 6.1, DTS-ES Matrix 6.1, DTS 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA-PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and DTS Neo:6
Various multichannel surround sound decoders are contained in ROM. For configurations of decoder algorithms, see Table 3 on Page 4.
Single-instruction multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI port, 6 serial ports, a Digital application interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisition port (PDAP), and 3 programmable timers, all under software control by the signal routing unit (SRU)
On-chip memory—up to 2M bits on-chip SRAM and a dedicated 4M bits on-chip mask-programmable ROM
The ADSP-2126x processors are available with a 150 MHz or a 200 MHz core instruction rate. For complete ordering information, see Ordering Guide on Page 45.
FEATURES
The ADSP-21262SKBCZ200 digital processor manufactured by Analog Devices can be implemented in electronics for faster and precise digital signal processing. This DSP processor has a minimum operating temperature of 0 °C and a maximum of 70 °C. 200 MHz is its maximum speed. Its rom program memory is 512KB. This device has a typical operating supply voltage of 1.2|3.3 V. Its minimum operating supply voltage of 1.14|3.13 V, while its maximum is 1.26|3.47 V. This is a 32 bit processor.
ECCN / UNSPSC
Description | Value |
USHTS: | 8542310001 |
CNHTS: | 8542319000 |
MXHTS: | 85423102 |
TARIC: | 8542319000 |
ECCN: | 3A991.a.2 |
Environmental & Export Classifications
Description | Value |
RoHS Status: | ROHS3 Compliant |
Moisture Sensitivity Level (MSL): | 3 (168 Hours) |
Documents & Media
Datasheets: | ADSP-21261/62/66 |
Design Resources: | Development Tool Selector |
Featured Product: | Analog Devices IoT and the Intelligence of Things |
Video File: | ADSP-21261/ADSP-21262 32-Bit Floating Point SHARC® DSPs |
HTML Datasheet: | SHARC Audio Module |
Other Related Documents: | SHARC Audio Module |
EDA / CAD Models: | SHARC Audio Module |
Online Catalog: | ADSP-21261/62/66 |
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- 5962-88565022A
- 88E1512-A0-NNP2C000
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- Product Attributes
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ADSP-21262SKBCZ200 Popularity by Region
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IC DSP CTLR 32BIT 136CSBGA
Manufacturer: | Analog Devices Inc. |
Series: | SHARC® |
Packaging: | Tray |
Part Status: | Active |
Type: | Floating Point |
Interface: | DAI SPI |
Clock Rate: | 200MHz |
Non-Volatile Memory: | ROM (512kB) |
On-Chip RAM: | 256kB |
Voltage - I/O: | 3.30V |
Voltage - Core: | 1.20V |
Operating Temperature: | 0°C ~ 70°C (TA) |
Mounting Type: | Surface Mount |
Package / Case: | 136-LFBGA CSPBGA |
Supplier Device Package: | 136-CSPBGA (12x12) |
Base Part Number: | ADSP-21262 |
Float-Pt Digital Signal Processor -Dsp, 32 Bit, 200Mhz, Bga-136:Newark
DSP Floating-Point 32-Bit 200MHz 200MIPS 136-Pin CSP-BGA:Avnet
The ADSP-21262 is the first member of the third-generation of SHARC® programmable DSPs. A range of applications such as high-quality audio and automotive entertainment systems, voice recognition, medical appliances and measurement devices benefit from the ADSP-21262’s integration of large on-chip memory with a wide variety of peripherals—thereby speeding time to market and keeping costs low. The ADSP-21262 is based on the SHARC DSP core that supports execution of 32-bit fixed-point and 32/40-bit floating-point arithmetic formats. With its core running at 200MHz (5 ns instruction cycle time), the ADSP-21262 is capable of executing complex Fast Fourier Transform (FFT) operations—1024-point complex FFT in 46us, more than 2.6x faster than comparatively priced processors. In audio applications, the single-instruction, multiple data (SIMD) mode effectively doubles the processor performance. The ADSP-21262 is designed with the highest level of integration, including 2 Mbit of on-chip dual-ported SRAM and 4 Mbit of mask programmable ROM memory. This large on-chip dual-ported memory enables sustained processor and I/O performance, without the need for external memory. System I/O is achieved through six full-duplex serial ports, four timers, a 16-bit parallel port, a serial peripheral interface (SPI), 22 zero-overhead Direct Memory Access (DMA) channels delivering fast data transfers without processor intervention and an innovative Digital Applications Interface (DAI) offering complete software control through its Signal Routing Unit (SRU). Digital Applications Interface (DAI) for Simplified I/O System Development The ADSP-21262 introduces the Digital Applications Interface (DAI), an architecture that enables complete software programmability of various peripherals. The flexibility and ease-of-use of the SHARC programming model, combined with the DAI, allow manufacturers to deploy one hardware configuration into multiple product offerings with different I/O requirements. Connections are made using the flexible Signal Routing Unit (SRU), a matrix routing group of pins that provides configurable and flexible connectivity between all DAI components and the SRU. The peripherals connected through the DAI are: a precision clock generator (PCG), an input data port (IDP), six SPORTS (serial ports), six flag inputs, six flag outputs, three timers and the SRU. The IDP provides an additional input path to the DSP core, configurable as 8 channels of receive serial data or as 7 channels of receive serial data and a single channel of up to a 20-bit wide parallel data. This level of integration enables the designer to take full advantage of a wide variety of peripherals without sacrificing the overall system performance. CROSSCORE Development Tools 3rd Generation SHARC DSP members are supported by ADI’s CROSSCORE brand of award winning development tools. The CROSSCORE components include the VisualDSP++™ software development environment, EZ-KIT Lite™ evaluation systems, and emulators. VisualDSP++ is an integrated software development environment, allowing for fast and easy development, debug, and deployment. The EZ-KIT Lite evaluation system provides an easy way to investigate the power of the ADI family of DSPs and begin to develop applications. Emulators are available for PCI and USB host platforms for rapid on-chip debugging. Additional development tools and algorithms are available from an extensive third-party development community.:Analog Devices
DSP Floating-Point 32-Bit 200MHz 200MIPS 136-Pin CSP-BGA:Avnet
The ADSP-21262 is the first member of the third-generation of SHARC® programmable DSPs. A range of applications such as high-quality audio and automotive entertainment systems, voice recognition, medical appliances and measurement devices benefit from the ADSP-21262’s integration of large on-chip memory with a wide variety of peripherals—thereby speeding time to market and keeping costs low. The ADSP-21262 is based on the SHARC DSP core that supports execution of 32-bit fixed-point and 32/40-bit floating-point arithmetic formats. With its core running at 200MHz (5 ns instruction cycle time), the ADSP-21262 is capable of executing complex Fast Fourier Transform (FFT) operations—1024-point complex FFT in 46us, more than 2.6x faster than comparatively priced processors. In audio applications, the single-instruction, multiple data (SIMD) mode effectively doubles the processor performance. The ADSP-21262 is designed with the highest level of integration, including 2 Mbit of on-chip dual-ported SRAM and 4 Mbit of mask programmable ROM memory. This large on-chip dual-ported memory enables sustained processor and I/O performance, without the need for external memory. System I/O is achieved through six full-duplex serial ports, four timers, a 16-bit parallel port, a serial peripheral interface (SPI), 22 zero-overhead Direct Memory Access (DMA) channels delivering fast data transfers without processor intervention and an innovative Digital Applications Interface (DAI) offering complete software control through its Signal Routing Unit (SRU). Digital Applications Interface (DAI) for Simplified I/O System Development The ADSP-21262 introduces the Digital Applications Interface (DAI), an architecture that enables complete software programmability of various peripherals. The flexibility and ease-of-use of the SHARC programming model, combined with the DAI, allow manufacturers to deploy one hardware configuration into multiple product offerings with different I/O requirements. Connections are made using the flexible Signal Routing Unit (SRU), a matrix routing group of pins that provides configurable and flexible connectivity between all DAI components and the SRU. The peripherals connected through the DAI are: a precision clock generator (PCG), an input data port (IDP), six SPORTS (serial ports), six flag inputs, six flag outputs, three timers and the SRU. The IDP provides an additional input path to the DSP core, configurable as 8 channels of receive serial data or as 7 channels of receive serial data and a single channel of up to a 20-bit wide parallel data. This level of integration enables the designer to take full advantage of a wide variety of peripherals without sacrificing the overall system performance. CROSSCORE Development Tools 3rd Generation SHARC DSP members are supported by ADI’s CROSSCORE brand of award winning development tools. The CROSSCORE components include the VisualDSP++™ software development environment, EZ-KIT Lite™ evaluation systems, and emulators. VisualDSP++ is an integrated software development environment, allowing for fast and easy development, debug, and deployment. The EZ-KIT Lite evaluation system provides an easy way to investigate the power of the ADI family of DSPs and begin to develop applications. Emulators are available for PCI and USB host platforms for rapid on-chip debugging. Additional development tools and algorithms are available from an extensive third-party development community.:Analog Devices
GENERAL DESCRIPTION
The ADSP-21261/ADSP-21262/ADSP-21266 SHARC® DSPs are members of the SIMD SHARC family of DSPs featuring Analog Devices, Inc., Super Harvard Architecture. The ADSP-2126x is source code compatible with the ADSP-21160 and ADSP-21161 DSPs as well as with first generation ADSP- 2106x SHARC processors in SISD (single-instruction, single data) mode. Like other SHARC DSPs, the ADSP-2126x are 32-bit/40-bit floating-point processors optimized for high performance audio applications with dual-ported on-chip SRAM, mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital application interface.SUMMARY
High performance 32-bit/40-bit floating-point processor optimized for high performance audio processingCode compatibility—at assembly level, uses the same instruction set as other SHARC DSPs
Processes high performance audio while enabling low system costs
Audio decoders and postprocessor algorithms support nonvolatile memory that can be configured to contain a combination of PCM 96 kHz, Dolby Digital, Dolby Digital Surround EX, DTS-ES Discrete 6.1, DTS-ES Matrix 6.1, DTS 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA-PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and DTS Neo:6
Various multichannel surround sound decoders are contained in ROM. For configurations of decoder algorithms, see Table 3 on Page 4.
Single-instruction multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI port, 6 serial ports, a Digital application interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisition port (PDAP), and 3 programmable timers, all under software control by the signal routing unit (SRU)
On-chip memory—up to 2M bits on-chip SRAM and a dedicated 4M bits on-chip mask-programmable ROM
The ADSP-2126x processors are available with a 150 MHz or a 200 MHz core instruction rate. For complete ordering information, see Ordering Guide on Page 45.
FEATURES
The ADSP-21262SKBCZ200 digital processor manufactured by Analog Devices can be implemented in electronics for faster and precise digital signal processing. This DSP processor has a minimum operating temperature of 0 °C and a maximum of 70 °C. 200 MHz is its maximum speed. Its rom program memory is 512KB. This device has a typical operating supply voltage of 1.2|3.3 V. Its minimum operating supply voltage of 1.14|3.13 V, while its maximum is 1.26|3.47 V. This is a 32 bit processor.
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