Product Overview
| Image: |
 |
| Manufacturer Part#: | ADSP-21161NCCAZ100 |
| Product Category: | Embedded - DSP (Digital Signal Processors) |
| Stock: | Yes |
| Manufacturer: | Analog devices inc. |
| Description: | IC DSP CONTROLLER 32BIT 225MBGA |
| Datasheet: | ADSP-21161N |
| Package: | 225-BGA, CSPBGA |
| Minimum: | 1 |
| Lead Time: | 3(168 Hours) |
| Quantity: | 90 PCS |
| Send RFQ: | Inquiry |
Reference Price
| Qty | Unit Price | Ext. Price |
| 1: | 56.35000 | 56.35000 |
| 10: | 529.33000 | 5293.30000 |
| 25: | 1280.63000 | 32015.75000 |
| 100: | 4951.75000 | 495175.00000 |
ADSP-21161NCCAZ100 Images are for reference only.
CAD Models
Product Attributes
| Manufacturer: | Analog devices inc． |
| Series: | Sharc® |
| Packaging: | Tray |
| Part status: | AcN/Ave |
| Type: | FloaN/Ang point |
| Interface: | Host interface link port serial port |
| Clock rate: | 100mhz |
| Non-volaN/Ale memory: | External |
| On-chip ram: | 128kb |
| Voltage - i/o: | 3．30v |
| Voltage - core: | 1．80v |
| OperaN/Ang temperature: | -40°c ~ 105°c (tc) |
| MounN/Ang type: | Surface mount |
| Package / case: | 225-bga cspbga |
| Supplier device package: | 225-cspbga (17x17) |
| Base part number: | Adsp-21161 |
Alternative Models
| Part | Compare | Manufacturers | Category | Description | |
| Mfr.Part#:ADSP-21161NCCAZ100 | Compare: Current Part | Manufacturers:Adi | Category:Digital Signal Processors(DSPs) | Description: Dsp floaN/Ang-point 32bit 100mhz 100mips 225pin csp-bga | |
| Mfr.Part#:ADSP-21161NKCAZ100 | Compare: ADSP-21161NCCAZ100 VS ADSP-21161NKCAZ100 | Manufacturers:Adi | Category:Digital Signal Processors(DSPs) | Description: Adsp-21161nkcaz100, 32bit digital signal processor 100mhz sdram, sram, 128kb ram, 225pin csp bga | |
| Mfr.Part#:ADSP-21161NCCA-100 | Compare: ADSP-21161NCCAZ100 VS ADSP-21161NCCA-100 | Manufacturers:Adi | Category:Digital Signal Processors(DSPs) | Description: Dsp floaN/Ang-point 32bit 100mhz 100mips 225pin csp-bga | |
| Mfr.Part#:ADSP-21161NYCAZ110 | Compare: ADSP-21161NCCAZ100 VS ADSP-21161NYCAZ110 | Manufacturers:Adi | Category:Digital Signal Processors(DSPs) | Description: Dsp floaN/Ang-point 32bit 100mhz 100mips 225pin csp-bga |
Descriptions
dsp floaN/Ang-point 32bit 100mhz 100mips 225-pin csp-bga tray:chip one stop japan
ic dsp controller 32bit 225mbga:digi-key
dsp, 32/40bit, 100mhz, bga-225:newark
the adsp-21161 sharc® dsp is the newest member of the super harvard architecture (sharc) family of programmable dsps. capable of 600 million math operaN/Aons per second (mflops), the adsp-21161 sets a new level of performance for low-cost sharc dsps - more than three N/Ames the performance for comparable models at about the same price. its road map includes a cost-effecN/Ave path to 1200 mflops for $5 per unit and a performance-driven path to 10 gflops and beyond. "this newest ediN/Aon to the sharc family will open more possibiliN/Aes for designers to design-in high performance digital signal processing into client-side applicaN/Aons and should help others reconsider applicaN/Aons they couldn’t do before with a single chip," said will strauss, president of forward concepts. "analog devices will certainly maintain customer loyalty with this road map." the adsp-21161 dsp is the second member of the sharc dsp family of 32-bit floaN/Ang-point programmable dsps to be based on a simd core architecture that is opN/Amized for digital signal processing performance. like all sharcs, the adsp-21161 is code-compaN/Able with all other members of the family and supports both fixed- and floaN/Ang-point data types. the adsp-21161 lowers the price for simd sharc dsp performance and is an outstanding dsp soluN/Aon for many price-sensiN/Ave applicaN/Aons. state-of-the-art development tools the adsp-21161, like all sharc processors, is supported by a complete set of software and hardware development tools. the visualdsp++® tool set offered by analog devices includes an opN/Amizing c/c++ compiler, integrated development environment (ide), assembler, linker, splitter and cycle accurate simulator that support both c and assembly debugging. emulaN/Aon support is jtag-based and adi offers usb, pci, and ethernet based emulators. sharc dsp roadmap there are two code-compaN/Able paths that the sharc dsp roadmap will follow. one opN/Amized for high-performance mulN/Aprocessing systems and the other for price/performance. performance is the key for mulN/Aprocessing applicaN/Aons and this is the reason that adi will offer 10 gflop sharc dsps in the future. on-chip memory sizes will be balanced to match this performance with memories increasing to unprecedented levels (64 mbit) using newly developed technologies. industry leading price/performance will be the driver on the other path of the roadmap. in the future, these sharc dsps will offer an increase in performance to 1200 mflops while decreasing price to as low as $5.00. this is required to support new technologies that demand substanN/Aal signal processing performance at consumer price points.:analog devices
ic dsp controller 32bit 225mbga:digi-key
dsp, 32/40bit, 100mhz, bga-225:newark
the adsp-21161 sharc® dsp is the newest member of the super harvard architecture (sharc) family of programmable dsps. capable of 600 million math operaN/Aons per second (mflops), the adsp-21161 sets a new level of performance for low-cost sharc dsps - more than three N/Ames the performance for comparable models at about the same price. its road map includes a cost-effecN/Ave path to 1200 mflops for $5 per unit and a performance-driven path to 10 gflops and beyond. "this newest ediN/Aon to the sharc family will open more possibiliN/Aes for designers to design-in high performance digital signal processing into client-side applicaN/Aons and should help others reconsider applicaN/Aons they couldn’t do before with a single chip," said will strauss, president of forward concepts. "analog devices will certainly maintain customer loyalty with this road map." the adsp-21161 dsp is the second member of the sharc dsp family of 32-bit floaN/Ang-point programmable dsps to be based on a simd core architecture that is opN/Amized for digital signal processing performance. like all sharcs, the adsp-21161 is code-compaN/Able with all other members of the family and supports both fixed- and floaN/Ang-point data types. the adsp-21161 lowers the price for simd sharc dsp performance and is an outstanding dsp soluN/Aon for many price-sensiN/Ave applicaN/Aons. state-of-the-art development tools the adsp-21161, like all sharc processors, is supported by a complete set of software and hardware development tools. the visualdsp++® tool set offered by analog devices includes an opN/Amizing c/c++ compiler, integrated development environment (ide), assembler, linker, splitter and cycle accurate simulator that support both c and assembly debugging. emulaN/Aon support is jtag-based and adi offers usb, pci, and ethernet based emulators. sharc dsp roadmap there are two code-compaN/Able paths that the sharc dsp roadmap will follow. one opN/Amized for high-performance mulN/Aprocessing systems and the other for price/performance. performance is the key for mulN/Aprocessing applicaN/Aons and this is the reason that adi will offer 10 gflop sharc dsps in the future. on-chip memory sizes will be balanced to match this performance with memories increasing to unprecedented levels (64 mbit) using newly developed technologies. industry leading price/performance will be the driver on the other path of the roadmap. in the future, these sharc dsps will offer an increase in performance to 1200 mflops while decreasing price to as low as $5.00. this is required to support new technologies that demand substanN/Aal signal processing performance at consumer price points.:analog devices
features
change from analog to digital with the adsp-21161nccaz100 digital signal processor from analog devices. this dsp processor has an operaN/Ang temperature range of -40 °c to 105 °c. 100 mhz is its maximum speed. this is a 32 bit processor. this device has a typical operaN/Ang supply voltage of 1.8|3.3 v. its minimum operaN/Ang supply voltage of 1.71|3.13 v, while its maximum is 1.89|3.47 v. it has romless program memory.
ECCN / UNSPSC
| Description | Value |
| Ushts: | 8542310001 |
| Cnhts: | 8542319000 |
| Mxhts: | 85423102 |
| Taric: | 8542319000 |
| Eccn: | 3a991.a.2 |
Environmental & Export Classifications
| Description | Value |
| Rohs status: | Rohs3 compliant |
| Moisture sensiN/Avity level (msl): | 3 (168 hours) |
Documents & Media
| Datasheets: | ADSP-21161N |
| Design Resources: | Development Tool Selector |
| Featured Product: | Analog Devices IoT and the Intelligence of Things |
| Video File: | SHARC Audio Module |
| Other Related Documents: | SHARC Audio Module |
| PCN Assembly/Origin: | SHARC Audio Module |
| EDA / CAD Models: | An Almost Pure DDS Sine Wave Tone Generator |
| Online Catalog: | ADSP-21161N Site Transfer 30/Apr/2020 |
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Ic dsp controller 32bit 225mbga
| Manufacturer: | Analog Devices Inc． |
| Series: | SHARC® |
| Packaging: | Tray |
| Part Status: | Active |
| Type: | Floating Point |
| Interface: | Host Interface Link Port Serial Port |
| Clock Rate: | 100MHz |
| Non-Volatile Memory: | External |
| On-Chip RAM: | 128kB |
| Voltage - I/O: | 3．30V |
| Voltage - Core: | 1．80V |
| Operating Temperature: | -40°C ~ 105°C (TC) |
| Mounting Type: | Surface Mount |
| Package / Case: | 225-BGA CSPBGA |
| Supplier Device Package: | 225-CSPBGA (17x17) |
| Base Part Number: | ADSP-21161 |
dsp floaN/Ang-point 32bit 100mhz 100mips 225-pin csp-bga tray:chip one stop japan
ic dsp controller 32bit 225mbga:digi-key
dsp, 32/40bit, 100mhz, bga-225:newark
the adsp-21161 sharc® dsp is the newest member of the super harvard architecture (sharc) family of programmable dsps. capable of 600 million math operaN/Aons per second (mflops), the adsp-21161 sets a new level of performance for low-cost sharc dsps - more than three N/Ames the performance for comparable models at about the same price. its road map includes a cost-effecN/Ave path to 1200 mflops for $5 per unit and a performance-driven path to 10 gflops and beyond. "this newest ediN/Aon to the sharc family will open more possibiliN/Aes for designers to design-in high performance digital signal processing into client-side applicaN/Aons and should help others reconsider applicaN/Aons they couldn’t do before with a single chip," said will strauss, president of forward concepts. "analog devices will certainly maintain customer loyalty with this road map." the adsp-21161 dsp is the second member of the sharc dsp family of 32-bit floaN/Ang-point programmable dsps to be based on a simd core architecture that is opN/Amized for digital signal processing performance. like all sharcs, the adsp-21161 is code-compaN/Able with all other members of the family and supports both fixed- and floaN/Ang-point data types. the adsp-21161 lowers the price for simd sharc dsp performance and is an outstanding dsp soluN/Aon for many price-sensiN/Ave applicaN/Aons. state-of-the-art development tools the adsp-21161, like all sharc processors, is supported by a complete set of software and hardware development tools. the visualdsp++® tool set offered by analog devices includes an opN/Amizing c/c++ compiler, integrated development environment (ide), assembler, linker, splitter and cycle accurate simulator that support both c and assembly debugging. emulaN/Aon support is jtag-based and adi offers usb, pci, and ethernet based emulators. sharc dsp roadmap there are two code-compaN/Able paths that the sharc dsp roadmap will follow. one opN/Amized for high-performance mulN/Aprocessing systems and the other for price/performance. performance is the key for mulN/Aprocessing applicaN/Aons and this is the reason that adi will offer 10 gflop sharc dsps in the future. on-chip memory sizes will be balanced to match this performance with memories increasing to unprecedented levels (64 mbit) using newly developed technologies. industry leading price/performance will be the driver on the other path of the roadmap. in the future, these sharc dsps will offer an increase in performance to 1200 mflops while decreasing price to as low as $5.00. this is required to support new technologies that demand substanN/Aal signal processing performance at consumer price points.:analog devices
ic dsp controller 32bit 225mbga:digi-key
dsp, 32/40bit, 100mhz, bga-225:newark
the adsp-21161 sharc® dsp is the newest member of the super harvard architecture (sharc) family of programmable dsps. capable of 600 million math operaN/Aons per second (mflops), the adsp-21161 sets a new level of performance for low-cost sharc dsps - more than three N/Ames the performance for comparable models at about the same price. its road map includes a cost-effecN/Ave path to 1200 mflops for $5 per unit and a performance-driven path to 10 gflops and beyond. "this newest ediN/Aon to the sharc family will open more possibiliN/Aes for designers to design-in high performance digital signal processing into client-side applicaN/Aons and should help others reconsider applicaN/Aons they couldn’t do before with a single chip," said will strauss, president of forward concepts. "analog devices will certainly maintain customer loyalty with this road map." the adsp-21161 dsp is the second member of the sharc dsp family of 32-bit floaN/Ang-point programmable dsps to be based on a simd core architecture that is opN/Amized for digital signal processing performance. like all sharcs, the adsp-21161 is code-compaN/Able with all other members of the family and supports both fixed- and floaN/Ang-point data types. the adsp-21161 lowers the price for simd sharc dsp performance and is an outstanding dsp soluN/Aon for many price-sensiN/Ave applicaN/Aons. state-of-the-art development tools the adsp-21161, like all sharc processors, is supported by a complete set of software and hardware development tools. the visualdsp++® tool set offered by analog devices includes an opN/Amizing c/c++ compiler, integrated development environment (ide), assembler, linker, splitter and cycle accurate simulator that support both c and assembly debugging. emulaN/Aon support is jtag-based and adi offers usb, pci, and ethernet based emulators. sharc dsp roadmap there are two code-compaN/Able paths that the sharc dsp roadmap will follow. one opN/Amized for high-performance mulN/Aprocessing systems and the other for price/performance. performance is the key for mulN/Aprocessing applicaN/Aons and this is the reason that adi will offer 10 gflop sharc dsps in the future. on-chip memory sizes will be balanced to match this performance with memories increasing to unprecedented levels (64 mbit) using newly developed technologies. industry leading price/performance will be the driver on the other path of the roadmap. in the future, these sharc dsps will offer an increase in performance to 1200 mflops while decreasing price to as low as $5.00. this is required to support new technologies that demand substanN/Aal signal processing performance at consumer price points.:analog devices
features
change from analog to digital with the adsp-21161nccaz100 digital signal processor from analog devices. this dsp processor has an operaN/Ang temperature range of -40 °c to 105 °c. 100 mhz is its maximum speed. this is a 32 bit processor. this device has a typical operaN/Ang supply voltage of 1.8|3.3 v. its minimum operaN/Ang supply voltage of 1.71|3.13 v, while its maximum is 1.89|3.47 v. it has romless program memory.
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