Product Overview
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Manufacturer Part#: | ADN2915ACPZ |
Product Category: | Clock/Timing - Application Specific |
Stock: | No |
Manufacturer: | Analog Devices Inc. |
Description: | IC CLK/DATA REC 6.5MBPS 24-LFCSP |
Datasheet: | ADN2915 Datasheet |
Package: | 24-VFQFN Exposed Pad, CSP |
Minimum: | 1 |
Lead Time: | 3(168 Hours) |
Quantity: | On Order |
Send RFQ: | Inquiry |
ADN2915ACPZ Images are for reference only.
Product Attributes
Manufacturer: | Analog Devices Inc. |
Series: | - |
Packaging: | Tray |
Part Status: | Active |
PLL: | Yes |
Main Purpose: | SONET/SDH |
Input: | CML |
Output: | CML |
Number of Circuits: | 1 |
Ratio - Input: | Output |
Differential - Input: | Output |
Frequency - Max: | 6.5Mbps |
Voltage - Supply: | 1.14V ~ 3.63V |
Operating Temperature: | -40°C ~ 85°C |
Mounting Type: | Surface Mount |
Package / Case: | 24-WFQFN Exposed Pad CSP |
Supplier Device Package: | 24-LFCSP-WQ (4x4) |
Base Part Number: | ADN2915 |
Alternative Models
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priceUSD 38.410 |
Max Supply Voltage3.63 V |
Min Supply Voltage1.14 V |
Logic Function- |
Interface- |
Max Frequency- |
Number of Pins24 |
Case/PackageLFCSP EP |
Authorized Distributors4 |
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priceUSD 25.580 |
Max Supply Voltage3.63 V |
Min Supply Voltage1.14 V |
Logic Function- |
Interface- |
Max Frequency- |
Number of Pins24 |
Case/PackageLFCSP EP |
Authorized Distributors5 |
Descriptions
Clock and Data Recovery 24-Pin LFCSP Tray:Avnet Europe
CLK/DATA RECOVERY, 176.8MHZ, LFCSP-24:element14 APAC
CDR 6.5Mbps to 11300Mbps SONET/SDH 24-Pin LFCSP EP Tray:Chip One Stop Global
IC CLK/DATA REC 6.5MBPS 24-LFCSP:Digi-Key
The ADN2915 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 6.5 Mbps to 11.3 Gbps. The ADN2915 automatically locks to all data rates without the need for an external reference clock or programming. ADN2915 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance. The ADN2915 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier, equalizer, or bypass at the input. The equalizer is either adaptive or can be manually set. The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers. The ADN2915 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. The ADN2915 is available in a compact 4 mm × 4 mm, 24-lead chip scale package (LFCSP). All ADN2915 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted. Applications SONET/SDH OC-1/OC-3/OC-12/OC-48/OC-192 and all associated FEC rates 1GFC, 2GFC, 4GFC, 8GFC, 10GFC, 1GE, and 10GE WDM transponders Any rate regenerators/repeaters:Analog Devices
CLK/DATA RECOVERY, 176.8MHZ, LFCSP-24:element14 APAC
CDR 6.5Mbps to 11300Mbps SONET/SDH 24-Pin LFCSP EP Tray:Chip One Stop Global
IC CLK/DATA REC 6.5MBPS 24-LFCSP:Digi-Key
The ADN2915 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 6.5 Mbps to 11.3 Gbps. The ADN2915 automatically locks to all data rates without the need for an external reference clock or programming. ADN2915 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance. The ADN2915 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier, equalizer, or bypass at the input. The equalizer is either adaptive or can be manually set. The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers. The ADN2915 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. The ADN2915 is available in a compact 4 mm × 4 mm, 24-lead chip scale package (LFCSP). All ADN2915 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted. Applications SONET/SDH OC-1/OC-3/OC-12/OC-48/OC-192 and all associated FEC rates 1GFC, 2GFC, 4GFC, 8GFC, 10GFC, 1GE, and 10GE WDM transponders Any rate regenerators/repeaters:Analog Devices
Environmental & Export Classifications
Description | Value |
RoHS Status: | ROHS3 Compliant |
Moisture Sensitivity Level (MSL): | 3 (168 Hours) |
Documents & Media
Datasheets: | ADN2915 Datasheet |
PCN Assembly/Origin: | Assembly Site Revision A 05/May/2014 |
Video File: | PLL Frequency Planning for Spurious Signal Elimination |
EDA / CAD Models: | Download from Ultra Librarian |
Online Catalog: | Optical Network |
Popularity by Region
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1. China100
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2. Germany75
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3. Taiwan74
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4. Lithuania69
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5. Iceland66
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6. Egypt65
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7. Portugal65
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8. Eritrea64
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9. Czech Republic64
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10. Antigua and Barbuda63
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11. Falkland Islands (Malvinas)63
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12. Japan63
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13. Mongolia63
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14. New Caledonia63
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15. Mexico62
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16. Montenegro62
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17. Russia61
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18. Ukraine61
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19. Estonia61
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20. Iraq61
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23. United States60
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24. Italy59
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30. Argentina59
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38. Cyprus57
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41. United Kingdom57
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42. Hong Kong57
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43. Switzerland57
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44. Netherlands57
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45. Australia57
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46. South Africa56
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48. Romania56
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70. Norway50
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71. North Macedonia49
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72. Greece48
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73. Yemen48
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74. Ireland45
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- Product Attributes
- Descriptions
- Features
- CAD Models
ADN2915ACPZ Popularity by Region
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IC CLK/DATA REC 6.5MBPS 24-LFCSP
Manufacturer: | Analog Devices Inc. |
Series: | - |
Packaging: | Tray |
Part Status: | Active |
PLL: | Yes |
Main Purpose: | SONET/SDH |
Input: | CML |
Output: | CML |
Number of Circuits: | 1 |
Ratio - Input: | Output |
Differential - Input: | Output |
Frequency - Max: | 6.5Mbps |
Voltage - Supply: | 1.14V ~ 3.63V |
Operating Temperature: | -40°C ~ 85°C |
Mounting Type: | Surface Mount |
Package / Case: | 24-WFQFN Exposed Pad CSP |
Supplier Device Package: | 24-LFCSP-WQ (4x4) |
Base Part Number: | ADN2915 |
Clock and Data Recovery 24-Pin LFCSP Tray:Avnet Europe
CLK/DATA RECOVERY, 176.8MHZ, LFCSP-24:element14 APAC
CDR 6.5Mbps to 11300Mbps SONET/SDH 24-Pin LFCSP EP Tray:Chip One Stop Global
IC CLK/DATA REC 6.5MBPS 24-LFCSP:Digi-Key
The ADN2915 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 6.5 Mbps to 11.3 Gbps. The ADN2915 automatically locks to all data rates without the need for an external reference clock or programming. ADN2915 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance. The ADN2915 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier, equalizer, or bypass at the input. The equalizer is either adaptive or can be manually set. The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers. The ADN2915 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. The ADN2915 is available in a compact 4 mm × 4 mm, 24-lead chip scale package (LFCSP). All ADN2915 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted. Applications SONET/SDH OC-1/OC-3/OC-12/OC-48/OC-192 and all associated FEC rates 1GFC, 2GFC, 4GFC, 8GFC, 10GFC, 1GE, and 10GE WDM transponders Any rate regenerators/repeaters:Analog Devices
CLK/DATA RECOVERY, 176.8MHZ, LFCSP-24:element14 APAC
CDR 6.5Mbps to 11300Mbps SONET/SDH 24-Pin LFCSP EP Tray:Chip One Stop Global
IC CLK/DATA REC 6.5MBPS 24-LFCSP:Digi-Key
The ADN2915 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 6.5 Mbps to 11.3 Gbps. The ADN2915 automatically locks to all data rates without the need for an external reference clock or programming. ADN2915 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance. The ADN2915 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier, equalizer, or bypass at the input. The equalizer is either adaptive or can be manually set. The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers. The ADN2915 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. The ADN2915 is available in a compact 4 mm × 4 mm, 24-lead chip scale package (LFCSP). All ADN2915 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted. Applications SONET/SDH OC-1/OC-3/OC-12/OC-48/OC-192 and all associated FEC rates 1GFC, 2GFC, 4GFC, 8GFC, 10GFC, 1GE, and 10GE WDM transponders Any rate regenerators/repeaters:Analog Devices
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There is no relevant information available for this part yet.