ADN2915ACPZ Datasheets | Clock/Timing - Application Specific IC CLK/DATA REC 6.5MBPS 24-LFCSP

Clock and Data Recovery 24-Pin LFCSP Tray:Avnet Europe
CLK/DATA RECOVERY, 176.8MHZ, LFCSP-24:element14 APAC
CDR 6.5Mbps to 11300Mbps SONET/SDH 24-Pin LFCSP EP Tray:Chip One Stop Global
IC CLK/DATA REC 6.5MBPS 24-LFCSP:Digi-Key
The ADN2915 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 6.5 Mbps to 11.3 Gbps. The ADN2915 automatically locks to all data rates without the need for an external reference clock or programming. ADN2915 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance. The ADN2915 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier, equalizer, or bypass at the input. The equalizer is either adaptive or can be manually set. The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers. The ADN2915 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. The ADN2915 is available in a compact 4 mm × 4 mm, 24-lead chip scale package (LFCSP). All ADN2915 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted. Applications SONET/SDH OC-1/OC-3/OC-12/OC-48/OC-192 and all associated FEC rates 1GFC, 2GFC, 4GFC, 8GFC, 10GFC, 1GE, and 10GE WDM transponders Any rate regenerators/repeaters:Analog Devices