Product Overview
| Image: |
 |
| Manufacturer Part#: | AD9517-0ABCPZ |
| Product Category: | Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers |
| Stock: | Yes |
| Manufacturer: | Analog devices inc. |
| Description: | IC CLOCK GEN 2.8GHZ VCO 48LFCSP |
| Datasheet: | AD9517-0 |
| Package: | 48-VFQFN Exposed Pad, CSP |
| Minimum: | 1 |
| Lead Time: | 3(168 Hours) |
| Quantity: | 1 PCS |
| Send RFQ: | Inquiry |
Reference Price
| Qty | Unit Price | Ext. Price |
| 1: | 14.41000 | 14.41000 |
| 10: | 13.24000 | 132.40000 |
| 25: | 12.69120 | 317.28000 |
| 100: | 11.18180 | 1118.18000 |
| 250: | 10.63300 | 2658.25000 |
| 500: | 9.94700 | 4973.50000 |
AD9517-0ABCPZ Images are for reference only.
CAD Models
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Product Attributes
| Manufacturer: | Analog devices inc． |
| Series: | - |
| Packaging: | Tray |
| Part status: | AcN/Ave |
| Type: | Clock generator fanout distribuN/Aon |
| Pll: | Yes |
| Input: | Cmos lvds lvpecl |
| Output: | Lvds lvpecl |
| Number of circuits: | 1 |
| RaN/Ao - input: | Output |
| DifferenN/Aal - input: | Output |
| Frequency - max: | 2．95ghz |
| Divider/mulN/Aplier: | Yes/no |
| Voltage - supply: | 3．135v ~ 3．465v |
| OperaN/Ang temperature: | -40°c ~ 85°c |
| MounN/Ang type: | Surface mount |
| Package / case: | 48-vfqfn exposed pad csp |
| Supplier device package: | 48-lfcsp-vq (7x7) |
| Base part number: | Ad9517 |
Alternative Models
| Part | Compare | Manufacturers | Category | Description | |
| Mfr.Part#:AD9517-0ABCPZ | Compare: Current Part | Manufacturers:Adi | Category:Clock & Timing | Description: Clock generator -40℃ to 85℃ 48pin lfcsp ep tray | |
| Mfr.Part#:AD9517-3ABCPZ-RL7 | Compare: AD9517-0ABCPZ VS AD9517-3ABCPZ-RL7 | Manufacturers:Adi | Category:Clock Generators | Description: Clock generator -40℃ to 85℃ 48pin lfcsp ep t/r | |
| Mfr.Part#:AD9517-3BCPZ | Compare: AD9517-0ABCPZ VS AD9517-3BCPZ | Manufacturers:Adi | Category:Clock & Timing | Description: Clock generator 48pin lfcsp ep tray | |
| Mfr.Part#:AD9517-0BCPZ | Compare: AD9517-0ABCPZ VS AD9517-0BCPZ | Manufacturers:Adi | Category:Clock & Timing | Description: Clock generator -40℃ to 85℃ 48pin lfcsp ep tray |
Descriptions
12-output clock generator with integrated 2.8 ghz vco | ic clock gen 2.8ghz vco 48lfcsp:win source electronics
clock generator 0mhz to 250mhz-in 2950mhz-out 48-pin lfcsp ep tray:verical
clock generator, 2.95ghz, lfcsp-48; clock ic type:clock generator; frequency:2.95ghz; no. of outputs:12outputs; supply voltage min:3.135v; supply voltage max:3.465v; clock ic case style:lfcsp; no. of pins:48pins rohs compliant: yes:newark
the ad9517-01 provides a mulN/A-output clock distribuN/Aon funcN/Aon with subpicosecond jitter performance, along with an on-chip pll and vco. the on-chip vco tunes from 2.55 ghz to 2.95 ghz. opN/Aonally, an external vco/vcxo of up to 2.4 ghz can be used. the ad9517-0 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applicaN/Aons with demanding phase noise and jitter requirements. the ad9517-0 features four lvpecl outputs (in two pairs) and four lvds outputs (in two pairs). each lvds output can be reconfigured as two cmos outputs. the lvpecl outputs operate to 1.6 ghz, the lvds outputs operate to 800 mhz, and the cmos outputs operate to 250 mhz. for applicaN/Aons that require addiN/Aonal outputs, a crystal reference input, zero-delay, or eeprom for automaN/Ac configuraN/Aon at startup, the ad9520 and ad9522 are available. in addiN/Aon, the ad9516 and ad9518 are similar to the ad9517 but have a different combinaN/Aon of outputs. each pair of outputs has dividers that allow both the divide raN/Ao and coarse delay (or phase) to be set. the range of division for the lvpecl outputs is 1 to 32. the lvds/cmos outputs allow a range of divisions up to a maximum of 1024. the ad9517-0 is available in a 48-lead lfcsp and can be operated from a single 3.3 v supply. an external vco, which requires an extended voltage range, can be accommodated by connecN/Ang the charge pump supply (vcp) to 5 v. a separate lvpecl power supply can be from 2.5 v to 3.3 v (nominal). the ad9517-0 is specified for operaN/Aon over the industrial range of −40°c to +85°c. applicaN/Aons low jitter, low phase noise clock distribuN/Aon 10/40/100 gb/sec networking line cards, including sonet, synchronous ethernet, otu2/3/4 forward error correcN/Aon (g.710) clocking high speed adcs, dacs, ddss, ddcs, ducs, mxfes high performance wireless transceivers ate and high performance instrumentaN/Aon 1ad9517 is used throughout to refer to all the members of the ad9517 family. however, when ad9517-0 is used, it is referring to that specific member of the ad9517 family.:analog devices
clock generator 0mhz to 250mhz-in 2950mhz-out 48-pin lfcsp ep tray:verical
clock generator, 2.95ghz, lfcsp-48; clock ic type:clock generator; frequency:2.95ghz; no. of outputs:12outputs; supply voltage min:3.135v; supply voltage max:3.465v; clock ic case style:lfcsp; no. of pins:48pins rohs compliant: yes:newark
the ad9517-01 provides a mulN/A-output clock distribuN/Aon funcN/Aon with subpicosecond jitter performance, along with an on-chip pll and vco. the on-chip vco tunes from 2.55 ghz to 2.95 ghz. opN/Aonally, an external vco/vcxo of up to 2.4 ghz can be used. the ad9517-0 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applicaN/Aons with demanding phase noise and jitter requirements. the ad9517-0 features four lvpecl outputs (in two pairs) and four lvds outputs (in two pairs). each lvds output can be reconfigured as two cmos outputs. the lvpecl outputs operate to 1.6 ghz, the lvds outputs operate to 800 mhz, and the cmos outputs operate to 250 mhz. for applicaN/Aons that require addiN/Aonal outputs, a crystal reference input, zero-delay, or eeprom for automaN/Ac configuraN/Aon at startup, the ad9520 and ad9522 are available. in addiN/Aon, the ad9516 and ad9518 are similar to the ad9517 but have a different combinaN/Aon of outputs. each pair of outputs has dividers that allow both the divide raN/Ao and coarse delay (or phase) to be set. the range of division for the lvpecl outputs is 1 to 32. the lvds/cmos outputs allow a range of divisions up to a maximum of 1024. the ad9517-0 is available in a 48-lead lfcsp and can be operated from a single 3.3 v supply. an external vco, which requires an extended voltage range, can be accommodated by connecN/Ang the charge pump supply (vcp) to 5 v. a separate lvpecl power supply can be from 2.5 v to 3.3 v (nominal). the ad9517-0 is specified for operaN/Aon over the industrial range of −40°c to +85°c. applicaN/Aons low jitter, low phase noise clock distribuN/Aon 10/40/100 gb/sec networking line cards, including sonet, synchronous ethernet, otu2/3/4 forward error correcN/Aon (g.710) clocking high speed adcs, dacs, ddss, ddcs, ducs, mxfes high performance wireless transceivers ate and high performance instrumentaN/Aon 1ad9517 is used throughout to refer to all the members of the ad9517 family. however, when ad9517-0 is used, it is referring to that specific member of the ad9517 family.:analog devices
ECCN / UNSPSC
| Description | Value |
| Ushts: | 8542390001 |
| Cnhts: | 8542319000 |
| Mxhts: | 85423901 |
| Taric: | 8542399000 |
| Eccn: | Ear99 |
Environmental & Export Classifications
| Description | Value |
| Rohs status: | Rohs3 compliant |
| Moisture sensiN/Avity level (msl): | 3 (168 hours) |
Documents & Media
| Datasheets: | AD9517-0 |
| Video File: | PLL Frequency Planning for Spurious Signal Elimination |
| Featured Product: | Explaining Phase Noise |
| PCN Assembly/Origin: | Interactive RF Signal Chain |
| EDA / CAD Models: | Mult Dev Assembly Chgs 21/Apr/2020 |
| Online Catalog: | Download from Ultra Librarian |
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Ic clock gen 2.8ghz vco 48lfcsp
| Manufacturer: | Analog Devices Inc． |
| Series: | - |
| Packaging: | Tray |
| Part Status: | Active |
| Type: | Clock Generator Fanout Distribution |
| PLL: | Yes |
| Input: | CMOS LVDS LVPECL |
| Output: | LVDS LVPECL |
| Number of Circuits: | 1 |
| Ratio - Input: | Output |
| Differential - Input: | Output |
| Frequency - Max: | 2．95GHz |
| Divider/Multiplier: | Yes/No |
| Voltage - Supply: | 3．135V ~ 3．465V |
| Operating Temperature: | -40°C ~ 85°C |
| Mounting Type: | Surface Mount |
| Package / Case: | 48-VFQFN Exposed Pad CSP |
| Supplier Device Package: | 48-LFCSP-VQ (7x7) |
| Base Part Number: | AD9517 |
12-output clock generator with integrated 2.8 ghz vco | ic clock gen 2.8ghz vco 48lfcsp:win source electronics
clock generator 0mhz to 250mhz-in 2950mhz-out 48-pin lfcsp ep tray:verical
clock generator, 2.95ghz, lfcsp-48; clock ic type:clock generator; frequency:2.95ghz; no. of outputs:12outputs; supply voltage min:3.135v; supply voltage max:3.465v; clock ic case style:lfcsp; no. of pins:48pins rohs compliant: yes:newark
the ad9517-01 provides a mulN/A-output clock distribuN/Aon funcN/Aon with subpicosecond jitter performance, along with an on-chip pll and vco. the on-chip vco tunes from 2.55 ghz to 2.95 ghz. opN/Aonally, an external vco/vcxo of up to 2.4 ghz can be used. the ad9517-0 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applicaN/Aons with demanding phase noise and jitter requirements. the ad9517-0 features four lvpecl outputs (in two pairs) and four lvds outputs (in two pairs). each lvds output can be reconfigured as two cmos outputs. the lvpecl outputs operate to 1.6 ghz, the lvds outputs operate to 800 mhz, and the cmos outputs operate to 250 mhz. for applicaN/Aons that require addiN/Aonal outputs, a crystal reference input, zero-delay, or eeprom for automaN/Ac configuraN/Aon at startup, the ad9520 and ad9522 are available. in addiN/Aon, the ad9516 and ad9518 are similar to the ad9517 but have a different combinaN/Aon of outputs. each pair of outputs has dividers that allow both the divide raN/Ao and coarse delay (or phase) to be set. the range of division for the lvpecl outputs is 1 to 32. the lvds/cmos outputs allow a range of divisions up to a maximum of 1024. the ad9517-0 is available in a 48-lead lfcsp and can be operated from a single 3.3 v supply. an external vco, which requires an extended voltage range, can be accommodated by connecN/Ang the charge pump supply (vcp) to 5 v. a separate lvpecl power supply can be from 2.5 v to 3.3 v (nominal). the ad9517-0 is specified for operaN/Aon over the industrial range of −40°c to +85°c. applicaN/Aons low jitter, low phase noise clock distribuN/Aon 10/40/100 gb/sec networking line cards, including sonet, synchronous ethernet, otu2/3/4 forward error correcN/Aon (g.710) clocking high speed adcs, dacs, ddss, ddcs, ducs, mxfes high performance wireless transceivers ate and high performance instrumentaN/Aon 1ad9517 is used throughout to refer to all the members of the ad9517 family. however, when ad9517-0 is used, it is referring to that specific member of the ad9517 family.:analog devices
clock generator 0mhz to 250mhz-in 2950mhz-out 48-pin lfcsp ep tray:verical
clock generator, 2.95ghz, lfcsp-48; clock ic type:clock generator; frequency:2.95ghz; no. of outputs:12outputs; supply voltage min:3.135v; supply voltage max:3.465v; clock ic case style:lfcsp; no. of pins:48pins rohs compliant: yes:newark
the ad9517-01 provides a mulN/A-output clock distribuN/Aon funcN/Aon with subpicosecond jitter performance, along with an on-chip pll and vco. the on-chip vco tunes from 2.55 ghz to 2.95 ghz. opN/Aonally, an external vco/vcxo of up to 2.4 ghz can be used. the ad9517-0 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applicaN/Aons with demanding phase noise and jitter requirements. the ad9517-0 features four lvpecl outputs (in two pairs) and four lvds outputs (in two pairs). each lvds output can be reconfigured as two cmos outputs. the lvpecl outputs operate to 1.6 ghz, the lvds outputs operate to 800 mhz, and the cmos outputs operate to 250 mhz. for applicaN/Aons that require addiN/Aonal outputs, a crystal reference input, zero-delay, or eeprom for automaN/Ac configuraN/Aon at startup, the ad9520 and ad9522 are available. in addiN/Aon, the ad9516 and ad9518 are similar to the ad9517 but have a different combinaN/Aon of outputs. each pair of outputs has dividers that allow both the divide raN/Ao and coarse delay (or phase) to be set. the range of division for the lvpecl outputs is 1 to 32. the lvds/cmos outputs allow a range of divisions up to a maximum of 1024. the ad9517-0 is available in a 48-lead lfcsp and can be operated from a single 3.3 v supply. an external vco, which requires an extended voltage range, can be accommodated by connecN/Ang the charge pump supply (vcp) to 5 v. a separate lvpecl power supply can be from 2.5 v to 3.3 v (nominal). the ad9517-0 is specified for operaN/Aon over the industrial range of −40°c to +85°c. applicaN/Aons low jitter, low phase noise clock distribuN/Aon 10/40/100 gb/sec networking line cards, including sonet, synchronous ethernet, otu2/3/4 forward error correcN/Aon (g.710) clocking high speed adcs, dacs, ddss, ddcs, ducs, mxfes high performance wireless transceivers ate and high performance instrumentaN/Aon 1ad9517 is used throughout to refer to all the members of the ad9517 family. however, when ad9517-0 is used, it is referring to that specific member of the ad9517 family.:analog devices
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