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How Does Computer Memory Work? Examples Analysis

Author: Apogeeweb Date: 6 Jul 2020  1862

type of computer memories

Ⅰ Introduction

Computer memory is used to store programs and data. The main function of memory is to read and write. For random access memory RAM, their main functions are to read and write, and for read-only memory ROM, the main function is only to read. In general, the memory can be a card,  a floppy disk, etc., they can be active or fixed, which used to access data.

This Video Introduce How Memory Store Data and How CPU Access Them.

Program is the basis of computer operation, and data is the object of computer operation. Regardless of whether it is a program or data, it is expressed in binary form in the memory, and is collectively referred to as information. In a computer, the memory capacity represents by byte (abbreviated as B) as the basic unit, a byte is composed of 8 binary bits. In addition to bytes, the storage capacity is expressed in KB, MB, GB, and TB (which may be referred to as K, M, G, and T, respectively. For example, 128MB may be referred to as 128M). Among them, 1KB=1024B, 1MB=1024KB, 1GB=1024MB, 1TB=1024GB.


Ⅰ Introduction

Ⅱ How to Store and Access Data?

Ⅲ What Computer Memory Do?

3.1 Explain Computer Memory

3.2 Binary Decoder

3.3 Chip Select & Bus

Ⅳ Example: 8086 Microprocessor

Ⅴ Technology Improvement

5.1 What is Direct Memory Access (DMA)?

5.2 DMA Transfer Modes

5.3 DMA Transfer Process

5.4 DMA Advantages and Disadvantages

Ⅵ Questions Related to Computer Memory Works

Ⅱ How to Store and Access Data?

Before you know how the electronic memory works, it is necessary to get a general idea of the normal computer operation.

Turn on the computer.

First, the computer loads data from ROM and executes a power-on self-test (POST) to ensure that all major components are working properly. As part of this test, fast read/write operations check all memory addresses to ensure that there are no errors in the memory chip by memory controller. Read-write operation means writing data to a certain bit and then reading from it.

Second, the computer loads the basic input/output system (BIOS) from the ROM. The BIOS provides the most basic information about storage devices, boot order, security, automatic identification functions, and other basic items.

The computer loads the operating system from the hard drive into the system RAM. Normally, as long as the computer is turned on, the critical part of the operating system is kept in RAM. This allows the CPU to immediately access the operating system, thereby enhancing the performance and functionality of the entire system.

Third, when an application is opened, it will be loaded into RAM. To save RAM space, only the basic part of the app programs are loaded, and then load other parts as needed. After the application is loaded, all files that have been opened for use in the RAM. When saving files and closing applications, files will be written to the designated storage device, and then the loading will be cleared from the RAM. It should be noted a fact that, if the changed files are not saved to the permanent storage device before being erased, they will be lost.

In the above operation, every time the content is loaded or opened, it is put into RAM. This only means that it has been put into the temporary storage area of computer so that the CPU can more easily access the information. The CPU requests the required data from the RAM, processes it, and then writes the new data back to the RAM with successive cycles. In most computers, data processing reached millions of times between the CPU and RAM per second.


Ⅲ What Computer Memory Do?

3.1 Explain Computer Memory

The memory is composed of a storage body, an address decoder, a read-write control circuit, an address bus, and a data bus.

A semiconductor memory is like a small drawer, and there are eight small grids in it. Each small grid is used to store charge. The charge is transferred in or discharged through the wire connected to it. It is easy to understand, if you think of a wire as a water pipe, and the electric charge in the small grid is like the water. Each small drawer in the memory is a place to store data, which we call a cell.

computer memory

Figure 1. Computer Memory

There are many cells in a memory, and the lines are connected in parallel. When the charge is applied, the charge will fill all the cells. When the charge is released, the charge in each cell will be discharged. This is of course not what we want. To avoid it, the memory structure should be changed slightly. There is a control line on each cell. Which unit you want to put the data, a signal is given to the control line of this unit. Be specific, this control line is like a switch, the charge can flow freely when switch on, and there is no signal on the control line of other cells to affect each other. So as long as you control the control lines of different cells, you can write different data to each unit. In the same way, if you want to get data from a unit, you only need to turn on the corresponding control line.


3.2 Binary Decoder


Figure 2. Decoder

First, how to control the control lines of each unit is not easy. For example, there are 655,36 units in a 27,512 memory chip, and each wire has to led out. This integrated circuit must have more than 60,000 pins. Obviously, this is clumsy. At this time, a way of decoding is made. Let’s briefly introduce it: a line can represent 2 states, 2 lines can represent 4 states, etc. And so on, 16 lines can be represented for 65536 states.


3.3 Chip Select & Bus

Next to the last question, let us focus on another problem. Where did the eight wires connect with each cell come from? In general, there are connected from the computer, and they also connect with other parts except for a memory chip. In this case, a problem arises. Since these eight lines are not dedicated between the memory and the computer, if you always connect a unit to these eight lines, this may cause confusion . For example, the value in a memory unit is 0FFH, in other memory cell is 00H, it is hard to figure out the high level or low level which these lines represent. So we have to separate them. The method is, when external wires are connected to the pins of the integrated circuit, they are not directly connected to each unit, and a group of switches is added between chip and computer. If we really want to write data to this memory or read data from the memory, then just turn on the switch. This group of switches is selected by three leads: read control end, write control end and chip select end.

To write data to the chip, first is selecting chip, then send out a write signal, and the switch is turn on, therefore, the data is written to the chip. If you want to read, first is selecting chip, then send the read signal, and the switch is closed, the data is sent out. In addition, the read and write signals should be connected to another memory. Since the chip select terminals are different, there is no conflict when having read or write operation. Many people still have a question, will these two chips be selected at the same time? As long as it is a well-designed system, it will not happen, because it is controlled by mathematical calculation, not a manual control. If there is a situation where two chips are selected at the same time, it may be a circuit failure.

It can be seen from the above that the eight lines used to transfer data are not dedicated, but are shared by many components, so we call them the data bus. The other 16 address lines are also connected together, called the address bus.


Ⅳ Example: 8086 Microprocessor

The CPU is connected to the storage unit and the I/O interface circuit through an address bus, a data bus, and a control bus. So how does the CPU access a certain address in the memory? Next, we will use the 8086 microprocessor architecture as an example, because its structure is simple and easy to introduce.


Figure 3. 8086 Microprocessor

If the CPU wants to read and write memory data, there must be wires to connect them together. In a computer, this kind of wire is called a bus. If you disassemble the computer case, it is easy to see that there is a collection of wires. These wires send signals at the same time, and each wire is either high or low level. The bus is divided into address bus, data bus and control bus according to different functions. Taking the above diagram as an example, the CPU needs to read the information at address 3, which is roughly divided into the following steps:

  • The CPU outputs the physical address 3 to the address line.
  • The control line needs to select the corresponding storage device, and then inform the device that data will be read from it.
  • The storage device will send data 8 to the data line.

8086 CPU Reading

Figure 4. 8086 CPU

From here we see that there is a bus connection between the CPU and the storage device. In fact, there is a bus inside the CPU. It connects different components, such as registers, operators, and controllers. But in the computer, the bit number of different buses is not necessarily the same. For example, the internal bus of the 8086 is 16-bit, the address bus is 20-bit, and the data bus is 16-bit.

Another question, since the 8086 CPU is a 16-bit structure, how can it output a 20-bit physical address? In fact, it is very simple. The address adder solves this way: segment address (16 bits) x 16 + offset address (16 bits) = physical address (20 bits), such as B800H x 16 + 1111H = B9000H. If you are not familiar with hexadecimal, then we can use decimal to describe this calculation. For example, home, school, and library are on a straight line. The distance between them is as shown in the following figure. Show the distance of the library: the library is 200m away from home, which is actually its physical address. But now there are some limits. We can only communicate with our friends through paper slips. Unfortunately, we can only write 2 digits on the papers, and the number of paper is not limited, so we agreed on the rule: paper 1x10+paper 2 = physical address, for example, write 11 on the paper 1 and 90 on the paper 2, which means that the school is 110m away from home and the library is 90m away from the school. The maximum distance that these two pieces of paper can represent is 99x10+99=1089.

The above mentioned is the concept of offset address of the segment address. Let's imagine that if the internal bus of the 8086 CPU is 20-bits, it can directly represent the physical address. Therefore, the concept of segment address is not critical here. What's more, the CPU hardware design will change in the future, and it may be completely different.

What we should know is how the CPU reads information from memory, and how does the CPU know whether the read information is ordinary data or a program that needs to be executed? We know that there are many registers in the CPU (that is used to store information), it specifies 2 registers, called CS, IP (CS is used to store the segment address, IP is used to store the offset address). They represent the physical address of the current machine code that needs to be executed. During the execution of the code, the CPU will maintain the values of CS and IP. For example, for each execution of the machine code, IP will increase the corresponding value to point to the next instruction. By analogy, we can use other registers to represent the physical address of the data. Therefore, the binary information in the memory has no difference to the CPU. Distinguishing the program and the data depends on the register.


Ⅴ Technology Improvement

Whether it is a PC card or the high-speed read-write disk in the storage system, we can not do data operation without the support of a hardware DMA.

8237 DMA

Figure 5. 8237 DMA Controller

5.1 What is Direct Memory Access (DMA)?

DMA refers to the interface technology that the external device directly exchanges data with the system memory without going through the CPU. It is a high-speed data transfer method that allows direct reading and writing of data between external devices and memory, neither through the CPU nor CPU intervention.

To read the data of the peripherals into the memory or transfer the data of the memory to the peripherals, it is generally done through CPU control, such as CPU program query or interrupt mode. Using interrupts for data transfer can greatly increase the CPU utilization. But it has shortcomings. For a high-speed I/O device and the case of batch exchange of data, the DMA method can be used to solve the efficiency and speed problems. DMA directly exchanges data between peripherals and memory, so the speed of data transfer depends on the working speed of the memory and peripherals.

The data transfer operation is performed under a "DMA controller". In addition to the CPU doing a little processing at the beginning and end, the CPU can execute other tasks during the transfer. In this way, the CPU and I/O are in parallel operation. Therefore, the efficiency of the computer system is greatly improved.

DMA Controller

Figure 6. DMA Controller

When realizing DMA transmission, the bus is directly controlled by the DMA controller. Therefore, there is a problem of bus control transfer. That is, before the DMA transfer, the CPU should hand over the bus control to the DMA controller, and after the transfer is done, the DMA controller should immediately return the bus control to the CPU.


5.2 DMA Transfer Modes

Peripherals can directly access the memory through the DMA controller, and at the same time, the CPU can continue to execute programs. So how does the DMA controller and CPU use memory in the same time? The following three modes are generally used:

(1) Burst mode: Stop the CPU access.

(2) Cycle stealing mode: DMA return the control of buses to CPU after transfer of one word at a time.

(3) Transparent mode: DMA and CPU access memory alternately.


  • Burst Mode

When the peripheral device requests to transfer a batch of data, the DMA controller sends a stop signal to the CPU, requesting the CPU to give up to use the address bus, data bus, and related control bus. After the DMA controller obtains the bus control right, it starts the data transfer. After a batch of data has been transferred, the DMA controller informs the CPU that it can use the memory and returns the bus control to it. Figure (a) is a time chart of this transmission method. Obviously, in this DMA transfer process, the CPU is basically in a non-working state or stands by.

Burst Mode

Advantage: It is suitable for group transmission of equipment requiring high data transmission rate.

Disadvantages: In the internal access stage of the DMA controller, the memory performance is not fully utilized, that is to say, a considerable part of the memory work cycle is idle. This is because the interval between two data transmitted by a peripheral device is generally always greater than the memory storage period, even for high-speed I/O devices. For example, a floppy disk requires about 32us to read an 8-bit binary number, and the storage period of semiconductor memory is less than 0.5us, so many idle storage periods cannot be used by the CPU.


  • Cycle Stealing Mode

When the I/O device has no DMA request, the CPU accesses the memory as required by the program. Once the I/O device executes a DMA request, one or several memory cycles will be embezzled.

The time sharing of this transmission mode is as follows: 

Cycle Stealing

1) At this time, the CPU does not need to access RAM, for example, the CPU is executing a multiplication instruction. Due to the long execution time of this instruction, there is no conflict between the I/O access and the CPU access, that is, the I/O device stealing one or two memory cycles has no effect on the CPU execution.

2) When the I/O device accesses, so does the CPU, which creates an access violation. In this case, the I/O device takes first, because it has an access time requirement, the previous I /O data must be accessed before the next request arrives. Obviously, the I/O device steals one or two memory cycles, which means that the CPU has delayed the execution of the instruction. More specifically, inserting a DMA request during the CPU's execution of the in-access instruction embezzles one or two memory cycles. Compared with the method of stopping CPU access, cycle stealing not only achieves I/O transfer, but also utilizes the efficiency of memory and CPU greatly. It is a win-win  method. However, I/O device diversion has the process of applying for bus control, establishing line control, and returning bus control. Transferring a word takes one cycle for RAM, but it is generally 2-5 memory cycles for DMA controllers (depending on the delay of the logic line). Therefore, the method is suitable for the case where the read/write cycle of the I/O device is greater than the RAM storage cycle.


  • Transparent Mode

If the CPU's work cycle is much longer than the memory access cycle, this method can make the highest efficiency of CPU and DMA access at the same time. Assuming that the CPU work cycle is 1.2μs and the memory access cycle is less than 0.6μs, then a CPU cycle can be divided into two sub-cycles, C1 and C2, where C1 is for DMA controller access and C2 is for CPU access.

The time sharing of this transmission method is as follows:

Transparent Mode


The following figure is the detailed time of DMA and CPU alternate accesses. C1 is dedicated to the DMA controller and C2 is dedicated to the CPU.

DMA and CPU Alternate Access Time


This method does not require the bus usage right. It is allocated through C1 and C2. The CPU and the DMA controller each have their own control registers such as internal address registers, data registers, and read/write signals. In the C1 cycle, if the DMA controller has an access request, it can send signals such as address and data to the bus. In the C2 cycle, if the CPU has an access request, it also do the same process. In fact, for the bus, this is a multiplexer controlled by C1 and C2. This transfer of bus control power takes almost no time, so the efficiency of DMA transfer is very high.

It is like transparent glass to the CPU, without any influence. Working in a transparent DMA mode, the CPU neither stops the main program running nor enters the stand-by state. It is an efficient working method, and the corresponding hardware logic is more complicated.


5.3 DMA Transfer Process

DMA Working Process

Figure 7. DMA Working Process

  • Request

The CPU initializes the DMA controller and gives an operation command to the I/O interface, then the I/O interface issues a DMA request.


  • Response

The DMA controller determines the priority and shielding of the DMA request, and makes a bus request to the bus adjudication logic. When the CPU executes the current bus cycle, the bus control can be released. At this time, the bus arbitration logic outputs a bus response, indicating that the DMA has responded, and notifies the I/O interface to take the DMA transfer through controller.


  • Transfer

After the DMA controller obtains the bus control right, the CPU immediately stops s or only performs internal operations. The DMA controller outputs read and write commands to control the RAM and I/O interface directly. Under the control of the DMA controller, the data is directly transferred between the memory and the external device. In addition, it is necessary to provide the starting position and length of the data to be transferred.


  • Rising an Interrupt

When the specified batch of data transfer is finished, the DMA controller releases the bus control right and sends an end signal to the I/O interface. When the I/O interface receives it, on the one hand, it stops the I/O device, on the other hand, it makes an interrupt request to the CPU. The CPU is free from the state of non-intervention, and performs a section to check the correctness of the DMA transfer operation code. Finally, the CPU will show the transfer result and carry out the original program.

It can be seen that the DMA transfer method does not require the CPU to directly control the transfer, nor does it have the process of retaining and restoring the scene when having the interrupt process. Through the hardware, a direct path for data transfer is opened for the RAM and I/O devices, that is DMA.


5.4 DMA Advantages and Disadvantages


DMA reduces the clock cycle requires to read or write a patch of data, which improve the system operation efficiency.


As a hardware device, running DMA control will increase cost.

DMA can cause cache coherence problem.



1. What is the purpose of computer memory?
Computer random access memory (RAM) is one of the most important components in determining your system's performance. RAM gives applications a place to store and access data on a short-term basis. It stores the information your computer is actively using so that it can be accessed quickly.


2. What is the role of memory in a computer system?
Computer memory or random access memory (RAM) is your system's short-term data storage; it stores the information your computer is actively using so that it can be accessed quickly. The more programs your system is running, the more memory you'll need.


3. Where is 8086 microprocessor used for?
8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and16 data lines that provides up to 1MB storage. It consists of powerful instruction set, which provides operations like multiplication and division easily.


4. How does direct memory access DMA work?
With DMA, the CPU first initiates the transfer, then it does other operations while the transfer is in progress, and it finally receives an interrupt from the DMA controller (DMAC) when the operation is done. ... DMA can also be used for "memory to memory" copying or moving of data within memory.


5. Why is DMA faster than CPU?
The direct memory access or DMA mode of data transfer is faster amongst all the mode of data transfer . ... The device request the cpu through a DMA controller to hold its data ,address and control bus so that the device may transfer data directly to or from memory.

Ordering & Quality

Photo Mfr. Part # Company Description Package PDF Qty Pricing
S29GL256S10TFI010 S29GL256S10TFI010 Company:Cypress Semiconductor Corp Remark:IC FLASH 256M PARALLEL 56TSOP Package:TSOP56
In Stock:221
1+: $6.19000
10+: $56.52000
25+: $138.61000
50+: $275.31000
100+: $493.95000
250+: $1230.13000
500+: $2306.69000
1000+: $4432.89000
24LC02BHT-E-OT 24LC02BHT-E-OT Company:Microchip Technology Remark:IC EEPROM 2K I2C 400KHZ SOT23-5 Package:SC-74A, SOT-753
In Stock:2951
1+: $0.26000
25+: $0.25000
100+: $0.24000
3000+: $0.24000
M95256-WMN6P M95256-WMN6P Company:STMicroelectronics Remark:EEPROM Memory IC 256Kb (32K x 8) SPI 20MHz 8-SO Package:8-SOIC (0.154"", 3.90mm Width)
In Stock:On Order
1+: $0.47000
10+: $0.46100
25+: $0.42840
50+: $0.42620
100+: $0.37840
250+: $0.37364
500+: $0.36798
1000+: $0.35815
5000+: $0.32196
CY7C1460AV25-200BZC CY7C1460AV25-200BZC Company:Cypress Semiconductor Corp Remark:36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL⑩ Architecture,SRAM 1Mx36 2.5V NoBL PL SRAM Package:165-LBGA
In Stock:On Order
24FC16-I-P 24FC16-I-P Company:Microchip Technology Remark:16KB I2C EEPROM, 1MHZ 1.7-5.5V, Package:8-DIP (0.300", 7.62mm)
In Stock:1060
1+: $0.34000
25+: $0.33000
100+: $0.31000
W25Q80DVSSIG W25Q80DVSSIG Company:Winbond Electronics Remark:IC FLASH 8M SPI 104MHZ 8SOIC Package:8-SOIC (0.209", 5.30mm Width)
In Stock:19527
1+: $0.42000
10+: $0.41100
25+: $0.38120
50+: $0.37920
100+: $0.33690
250+: $0.33252
500+: $0.32756
1000+: $0.31879
5000+: $0.28653
AT24C1024BN-SH25-B AT24C1024BN-SH25-B Company:Microchip Technology Remark:IC EEPROM 1M I2C 1MHZ 8SOIC Package:8-SOIC (0.154", 3.90mm Width)
In Stock:On Order
AT27C4096-90JU AT27C4096-90JU Company:Microchip Technology Remark:IC EPROM 4M PARALLEL 44PLCC Package:44-LCC (J-Lead)
In Stock:116
1+: $6.80000
25+: $6.55000
100+: $6.29000

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