The 1Gb DDR2 SDRAM is organized asa 32Mbit x 4 I/Os x 8banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for general applications. Key Features • JEDEC standard VDD= 1.8V ± 0.1V Power Supply •VDDQ= 1.8V ± 0.1V • 333MHz fCKfor 667Mb/sec/pin, 400MHz fCKfor 800Mb/sec/pin • 8 Banks • Posted CAS • Programmable CASLatency: 3, 4, 5, 6 • Programmable Additive Latenc y: 0, 1, 2, 3, 4, 5 • Write Latency(WL) = Read Latency(RL) -1 • Burst Length: 4 , 8(Interleave/nibble sequential) • Programmable Sequential / Interleave Burst Mode • Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) • Off-Chip Driver(OCD) Impedance Adjustment • On Die Termination • Special Function Support - 50ohm ODT - High Temperature Self-Refresh rate enable • Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE <95 °C • All of products are Lead-Free, Halogen-Free, and RoHS compliant
GENERAL DESCRIPTION The W971GG6JB is a 1G bits DDR2 SDRAM, organized as 8,388,608 words 8 banks 16 bits. This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for various applications. W971GG6JB is sorted into the following grade parts: -18, -25, 25L, 25I, 25A, 25K, -3 and -3A. The -18 grade parts is compliant to the DDR2-1066 (6-6-6) specification. The -25/25L/25I/25A/25K grade parts are compliant to the DDR2-800 (5-5-5) specification (the 25L grade parts is guaranteed to support IDD2P = 7 mA and IDD6 = 4 mA at commercial temperature, the 25I industrial grade parts is guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -3/-3A grade parts is compliant to the DDR2-667 (5-5-5) specification. FEATURES Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V Double Data Rate architecture: two data transfers per clock cycle CAS Latency: 3, 4, 5, 6 and 7 Burst Length: 4 and 8 Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data Edge-aligned with Read data and center-aligned with Write data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CLK and CLK) Data masks (DM) for write data Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS Posted CAS programmable additive latency supported to make command and data bus efficiency Read Latency = Additive Latency plus CAS Latency (RL = AL + CL) Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality Auto-precharge operation for read and write bursts Auto Refresh and Self Refresh modes Precharged Power Down and Active Power Down Write Data Mask Write Latency = Read Latency - 1 (WL = RL - 1) Interface: SSTL_18 Packaged in WBGA 84 Ball (8X12.5 mm2), using Lead free materials with RoHS compliant