The SN74LVC16245ADGGR is a 16-bit (dual-octal) non-inverting Bus Transceiver with 3-state outputs. This device is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control input. The output-enable input can be used to disable the device so that the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LVCH16245ADGGR is a 16-bit non-inverting Bus Transceiver with 3-state outputs and designed for 1.65 to 3.6V VCC operation. This device is designed for asynchronous communication between data buses. This device can be used as two 8-bit transceivers or one 16-bit transceiver. Active bus-hold circuitry holds unused or un-driven data inputs at a valid logic state. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. Active bus-hold circuitry holds unused or un-driven data inputs at a valid logic state. Use of pull-up/pull-down resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE or DIR.
DESCRIPTION The 74LCX16245 is a low voltage CMOS 16 BITBUS TRANSCEIVER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. This IC is intended for two-way asynchronous communication between data buses; the direction of data transmission is determined by DIR input. The two enable inputs nG can be used to disable the device so that the buses are effectively isolated. ■ 5V TOLERANT INPUTS AND OUTPUTS ■ HIGH SPEED : tPD= 4.5 ns (MAX.) at VCC=3V ■ POWER DOWN PROTECTION ON INPUTS AND OUTPUTS ■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH|=IOL= 24mA (MIN) at VCC=3V ■ PCI BUS LEVELS GUARANTEED AT 24 mA ■ BALANCED PROPAGATION DELAYS: tPLH≅t PHL ■ OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) ■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16245 ■ LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ■ ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V