General Description This quad receiver is designed for high speed interconnect utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. The FIN1048 can be paired with its companion driver, the FIN1047, or any other LVDS driver. Features ■ Greater than 400Mbs data rate ■ Flow-through pinout simplifies PCB layout ■ 3.3V power supply operation ■ 0.4ns maximum differential pulse skew ■ 2.5ns maximum propagation delay ■ Low power dissipation ■ Power-Off protection ■ Fail safe protection for open-circuit, shorted and terminated conditions ■ Meets or exceeds the TIA/EIA-644 LVDS standard ■ Pin compatible with equivalent RS-422 and LVPECL devices ■ 16-Lead SOIC and TSSOP packages save space
The SN65LVDS31D is a high-speed differential Line Driver implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds and allow operation with a 3.3V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247mV into a 100R load when enabled. The intended application of this device and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100R. The transmission media may be printed-circuit board traces, backplanes or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
DESCRIPTION This family of four-, eight-, or sixteen-, differential line receivers (with optional integrated termination) im plements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. FEATURES • Four- ("390), Eight- ("388A), or Sixteen- ("386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard • Integrated 110-Ω Line Termination Resistors on LVDT Products • Designed for Signaling Rates(1) Up To 630 Mbps • SN65 Version"s Bus-Terminal ESD Exceeds 15 kV • Operates From a Single 3.3-V Supply • Typical Propagation Delay Time of 2.6 ns • Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns • LVTTL Levels Are 5-V Tolerant • Open-Circuit Fail Safe • Flow-Through Pinout • Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch