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EPM3128ATC100-10 vs EPM3128ATC100-7N vs EPM3128ATC100-10N Comparison

  • Hide Shared Attributes
    EPM3128ATC100-10
    EPM3128ATC100-10
    EPM3128ATC100-7N
    EPM3128ATC100-7N
    EPM3128ATC100-10N
    EPM3128ATC100-10N
  • Part No.
    EPM3128ATC100-10
    EPM3128ATC100-7N
    EPM3128ATC100-10N
  • Description
    CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz CMOS Technology 3.3V 100Pin TQFP
    CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 129.9MHz CMOS Technology 3.3V 100Pin TQFP
    CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz CMOS Technology 3.3V 100Pin TQFP
  • Manufacturer
    Altera
    Altera
    Altera
  • Classification
    CPLDs
    CPLDs
    CPLDs
  • Reference Price(USD)
    $9.355
    $28.012
    $3.073
  • Inventory(pcs)
    0
    0
    0
  • Case/Package
    TQFP-100
    TQFP-100
    TQFP-100
  • Number of Pins
    100
    100
    100
  • Number of I/O Pins
    80
    80
    80
  • Frequency
    -
    129.9 MHz
    98 MHz
  • Number of Gates
    -
    2500
    2500
  • Number of Positions
    -
    100
    100
  • ECCN Code
    EAR99
    -
    EAR99
  • HK STC License
    NLR
    NLR
    NLR
  • Supply Voltage (DC)
    3.30 V
    3.30 V
    3.30 V
  • Operating Temperature
    0℃ ~ 70℃
    0℃ ~ 70℃ (TA)
    0℃ ~ 70℃
  • Size-Length
    -
    -
    14 mm
  • Size-Width
    -
    -
    14 mm
  • Size-Height
    1 mm
    1 mm
    1 mm
  • Mounting Style
    Surface Mount
    Surface Mount
    Surface Mount
  • Packaging
    Tray
    Tray
    Tray
  • REACH SVHC Compliance
    -
    No SVHC
    No SVHC
  • Lead-Free Status
    Contains Lead
    Lead Free
    Lead Free
  • RoHS
    Non-Compliant
    RoHS Compliant
    RoHS Compliant
  • Product Lifecycle Status
    Last Time Buy
    Active
    Active
  • Supply Voltage (Min)
    3 V
    3 V
    3 V
  • Supply Voltage
    3.3 V
    3.3 V
    3.3 V
  • Supply Voltage (Max)
    3.6 V
    3.6 V
    3.6 V
  • Industrial-Spec
    -
    -
    Yes
  • Operating Temperature (Max)
    70 ℃
    70 ℃
    70 ℃
  • Number of Inputs and Outputs
    -
    80
    80 Input
  • Operating Temperature (Min)
    0 ℃
    0 ℃
    0 ℃
  • REACH SVHC Compliance Edition
    -
    2015/12/17
    2014/06/16
  • Overview
    EPM3128ATC100-10 Product overview

    General Description MAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricatedwith advanced CMOS technology, the EEPROM–based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2. Features... ■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1) ■ 3.3-V in-system programmability(ISP) through the built–in IEEE Std. 1149.1 Joint Test ActionGroup (JTAG) interface with advanced pin-locking capability     – ISP circuitry compliant with IEEE Std. 1532 ■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 ■ Enhanced ISP features:     – Enhanced ISP algorithm for faster programming     – ISP_Done bit to ensure complete programming     – Pull-up resistor on I/O pinsduring in–system programming ■ High–density PLDs ranging from 600 to 10,000 usable gates ■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz ■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels ■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages ■ Hot–socketing support ■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance ■ Industrial temperature range ■ PCI compatible ■ Bus–friendly architecture including programmable slew–rate control ■ Open–drain output option ■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls ■ Programmable power–saving mode for a power reduction of over 50%in each macrocell ■ Configurable expander product–term distribution, allowing up to 32 product terms per macrocell ■ Programmable security bit for protection of proprietary designs ■ Enhanced architectural features, including:     – 6 or 10 pin– or logic–driven output enable signals     – Two global clock signals with optional inversion     – Enhanced interconnect resources for improved routability     – Programmable output slew–rate control ■ Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest ■ Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third–party manufacturers and any in–circuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf)

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    EPM3128ATC100-10N Product overview

    The EPM3128ATC100-10N is an EEPROM Complex Programmable Logic Device with 2500 usable gates and 128 macro cells. MAX 3000A CPLD is a high-performance, CMOS EEPROM-based programmable logic devices (PLDs) built on a MAX® architecture. Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance. The MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density small-scale integration (SSI), medium-scale integration (MSI) and large-scale integration (LSI) logic functions.

    .
    Enhanced ISP algorithm for faster programming
    .
    Hot-socketing support
    .
    PCI compatible
    .
    Bus-friendly architecture including programmable slew-rate control
    .
    Open-drain output option
    .
    Programmable power-saving mode for a power reduction of over 50% in each macro cell
    .
    Programmable security bit for protection of proprietary designs
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EPM3128ATC100-7N Alternative Parts

Image Part Compare Manufacturer Category Description
Image:EPM3128ATC100-7N Mfr.Part#:EPM3128ATC100-7N Compare: Current Part Manufacturers:Altera Category:CPLDs Description:CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 129.9MHz CMOS Technology 3.3V 100Pin TQFP
Image:EPM3128ATC100-10 Mfr.Part#:EPM3128ATC100-10 Compare: EPM3128ATC100-7N VS EPM3128ATC100-10 Manufacturers:Altera Category:CPLDs Description:CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz CMOS Technology 3.3V 100Pin TQFP
Image:EPM3128ATC100-7 Mfr.Part#:EPM3128ATC100-7 Compare: EPM3128ATC100-7N VS EPM3128ATC100-7 Manufacturers:Altera Category:CPLDs Description:CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 129.9MHz CMOS Technology 3.3V 100Pin TQFP
Image:EPM3128ATC100-10N Mfr.Part#:EPM3128ATC100-10N Compare: EPM3128ATC100-7N VS EPM3128ATC100-10N Manufacturers:Altera Category:CPLDs Description:CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz CMOS Technology 3.3V 100Pin TQFP