The DS90C365AMT is a Transmitter converts 21-bits of LVCMOS/LVTTL data into four LVDS (low voltage differential signalling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over the fourth LVDS link. Every cycle of the transmit clock 21-bits RGB of input data are sampled and transmitted. At a transmit clock frequency of 87.5MHz, 21-bits of RGB data and 3-bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 612.5Mbps per LVDS data channel. Using a 87.5MHz clock, the data throughput is 229.687Mbps. This transmitter can be programmed for Rising edge strobe or falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe FPDLink Receiver without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces with added spread spectrum clocking support.
DESCRIPTION The DS90C365A is a pin to pin compatible replacement for DS90C363, DS90C363A and DS90C365. The DS90C365A has additional features and improvements making it an ideal replacement for DS90C363, DS90C363A and DS90C365. family of LVDS Transmitters. FEATURES • Pin-to-pin compatible to DS90C363, DS90C363A and DS90C365 • No special start-up sequence required between clock/data and /PD pins. Input signals (clock and data) can be applied either before or after the device is powered. • Support Spread Spectrum Clocking up to 100kHz frequency modulation & deviations of ±2.5% center spread or -5% down spread. • “Input Clock Detection” feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high. • 18 to 87.5 MHz shift clock support • Tx power consumption < 146 mW (typ) at 87.5 MHz Grayscale • Tx Power-down mode < 37 uW (typ) • Supports VGA, SVGA, XGA, SXGA (dual pixel), SXGA+ (dual pixel), UXGA (dual pixel). • Narrow bus reduces cable size and cost • Up to 1.785 Gbps throughput • Up to 223.125 Megabytes/sec bandwidth • 345 mV (typ) swing LVDS devices for low EMI • PLL requires no external components • Compliant to TIA/EIA-644 LVDS standard • Low profile 48-lead TSSOP package
The SN75LVDS84A and SN65LVDS84AQ FlatLink transmitters contains three 7-bit parallel-load serial-out shift registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A. When transmitting, data bits D0 - D20 are each loaded into registers of the "LVDS84A upon the falling edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The "LVDS84A requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN\\\\) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low level. The SN75LVDS84A is characterized for operation over ambient free-air temperatures of 0°C to 70°C. The SN65LVDS84AQ is characterized for operation over the full Automotive temperature range of -40°C to 125°C. View datasheet View product folder