SRAM - Asynchronous Memory IC 16Mb (1M x 16) Parallel 10ns 54-TSOP II
The CY7C1061AV33-10ZXI is a 16MB high performance CMOS Static Random Access Memory (SRAM) organized as 1048576 words by 16-bit. To write to the device, enable the chip while forcing the write enable input LOW. If byte low enable is LOW, then data from I/O pins, is written into the location specified on the address pins. If byte high enable is LOW, then data from I/O pins is written into the location specified on the address pins. To read from the device, enable the chip by taking CE1 LOW and CE2 HIGH while forcing the output enable LOW and the write enable HIGH. If byte low enable is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If byte high enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. The input/output pins are placed in a high-impedance state when the device is deselected, the outputs are disabled, the BHE and BLE are disabled or a write operation is in progress.