Home  CY37256P160-125AC  CY37256P160-125AC VS CY37256P160-83AXC

CY37256P160-125AC vs CY37256P160-125AXI vs CY37256P160-83AXC Comparison

  • Hide Shared Attributes
    CY37256P160-125AC
    CY37256P160-125AC
    CY37256P160-125AXI
    CY37256P160-125AXI
    CY37256P160-83AXC
    CY37256P160-83AXC
  • Part No.
    CY37256P160-125AC
    CY37256P160-125AXI
    CY37256P160-83AXC
  • Description
    IC CPLD 256MC 10NS 160LQFP
    CPLD Ultra37000 Family 7.7K Gates 256 Macro Cells 125MHz CMOS Technology 5V 160Pin TQFP
    CPLD Ultra37000 Family 7.7K Gates 256 Macro Cells 83MHz CMOS Technology 5V 160Pin TQFP
  • Manufacturer
    Cypress semiconductor
    Cypress semiconductor
    Cypress semiconductor
  • Classification
    CPLDs
    CPLDs
    CPLDs
  • Reference Price(USD)
    -
    $160.725
    $59.542
  • Inventory(pcs)
    841
    0
    2.2k
  • Case/Package
    LQFP-160
    TQFP-160
    TQFP-160
  • Number of Pins
    160
    160
    160
  • Number of I/O Pins
    133
    133
    133
  • Frequency
    -
    125 MHz
    -
  • Supply Voltage (DC)
    5.00 V
    5.00 V
    5.00 V
  • Operating Temperature
    0℃ ~ 70℃ (TA)
    -40℃ ~ 85℃
    0℃ ~ 70℃ (TA)
  • Size-Length
    -
    -
    24 mm
  • Size-Width
    -
    -
    24 mm
  • Size-Height
    -
    -
    1.4 mm
  • Mounting Style
    Surface Mount
    Surface Mount
    Surface Mount
  • Packaging
    Tray
    Tray
    Tray
  • Lead-Free Status
    Contains Lead
    Lead Free
    Lead Free
  • RoHS
    Non-Compliant
    RoHS Compliant
    RoHS Compliant
  • Product Lifecycle Status
    Unknown
    Unknown
    Unknown
  • Operating Temperature (Max)
    -
    85 ℃
    70 ℃
  • Operating Temperature (Min)
    -
    -40 ℃
    0 ℃
  • Supply Voltage
    -
    5 V
    -
  • Supply Voltage (Max)
    -
    -
    5.25 V
  • Supply Voltage (Min)
    -
    -
    4.75 V
  • Overview
    CY37256P160-125AC Product overview

    General Description The Ultra37000™ family of CMOSCPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The Ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins • Simple timing model — No fanout delays — No expander delays — No dedicated vs. I/O pin delays — No additional delay through PIM — No penalty for using full 16 product terms — No delay for steering or sharing product terms • 3.3V and 5V versions • PCI-compatible[1] • Programmable bus-hold capabilities on all I/Os • Intelligent product term allocator provides: — 0 to 16 product terms to any macrocell — Product term steering onan individual basis — Product term sharing among local macrocells • Flexible clocking — Four synchronous clocks per device — Product term clocking — Clock polarity control per logic block • Consistent package/pinout offering across all densities — Simplifies design migration — Same pinout for 3.3V and 5.0V devices • Packages — 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages — Lead(Pb)-free packages available

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    CY37256P160-125AXI Product overview

    General Description The Ultra37000™ family of CMOSCPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The Ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins • Simple timing model — No fanout delays — No expander delays — No dedicated vs. I/O pin delays — No additional delay through PIM — No penalty for using full 16 product terms — No delay for steering or sharing product terms • 3.3V and 5V versions • PCI-compatible[1] • Programmable bus-hold capabilities on all I/Os • Intelligent product term allocator provides: — 0 to 16 product terms to any macrocell — Product term steering onan individual basis — Product term sharing among local macrocells • Flexible clocking — Four synchronous clocks per device — Product term clocking — Clock polarity control per logic block • Consistent package/pinout offering across all densities — Simplifies design migration — Same pinout for 3.3V and 5.0V devices • Packages — 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages — Lead(Pb)-free packages available

    View all
    CY37256P160-83AXC Product overview

    General Description The Ultra37000™ family of CMOSCPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The Ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins • Simple timing model — No fanout delays — No expander delays — No dedicated vs. I/O pin delays — No additional delay through PIM — No penalty for using full 16 product terms — No delay for steering or sharing product terms • 3.3V and 5V versions • PCI-compatible[1] • Programmable bus-hold capabilities on all I/Os • Intelligent product term allocator provides: — 0 to 16 product terms to any macrocell — Product term steering onan individual basis — Product term sharing among local macrocells • Flexible clocking — Four synchronous clocks per device — Product term clocking — Clock polarity control per logic block • Consistent package/pinout offering across all densities — Simplifies design migration — Same pinout for 3.3V and 5.0V devices • Packages — 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages — Lead(Pb)-free packages available

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CY37256P160-125AC Alternative Parts

Image Part Compare Manufacturer Category Description
Image:CY37256P160-125AC Mfr.Part#:CY37256P160-125AC Compare: Current Part Manufacturers:Cypress semiconductor Category:CPLDs Description:Ic cpld 256mc 10ns 160lqfp
Image:CY37256P160-125AXC Mfr.Part#:CY37256P160-125AXC Compare: CY37256P160-125AC VS CY37256P160-125AXC Manufacturers:Cypress semiconductor Category:CPLDs Description:Cpld ultra37000 family 7.7k gates 256 macro cells 125mhz cmos technology 5v 160pin tqfp
Image:CY37256P160-125AXI Mfr.Part#:CY37256P160-125AXI Compare: CY37256P160-125AC VS CY37256P160-125AXI Manufacturers:Cypress semiconductor Category:CPLDs Description:Cpld ultra37000 family 7.7k gates 256 macro cells 125mhz cmos technology 5v 160pin tqfp
Image:CY37256P160-83AXC Mfr.Part#:CY37256P160-83AXC Compare: CY37256P160-125AC VS CY37256P160-83AXC Manufacturers:Cypress semiconductor Category:CPLDs Description:Cpld ultra37000 family 7.7k gates 256 macro cells 83mhz cmos technology 5v 160pin tqfp