The CD54HC245, CD54HCT245, and CD74HC245, CD74HCT245 are high-speed octal three-state bidirectional transceivers intended for two-way asynchronous communication between data buses. They have high drive current outputs which enable high-speed operation while driving large bus capacitances. They provide the low power consumption of standard CMOS circuits with speeds and drive capabilities comparable to that of LSTTL circuits. The CD54HC245, CD54HCT245, CD74HC245 and CD74HCT245 allow data transmission of the B bus or from the B bus to the A bus. The logic level at the direction input (DIR) determines the direction. The output enable input (OE\\\\), when high, puts the I/O ports in the high-impedance state. The HC/HCT245 is similar in operation to the HC/HCT640 and the HC/HCT643.
The MC74HCT245ADWG is an octal high-performance silicon-gate CMOS Non-inverting Bus Transceiver with LSTTL compatible inputs. The MC74HCT245A is identical in pin-out to the LS245. This device may be used as a level converter for interfacing TTL or NMOS outputs to high speed CMOS inputs. The MC74HCT245A is a 3-state non-inverting transceiver that is used for 2-way asynchronous communication between data buses. The device has an active-low output enable pin, which is used to place the I/O ports into high-impedance states. The direction control determines whether data flows from A to B or from B to A.
The MM74HCT245WMX is an octal 3-state bidirectional Buffer Transceiver utilizes advanced silicon-gate CMOS technology and is intended for two-way asynchronous communication between data buses. It has high drive current outputs which enable high speed operation even when driving large bus capacitances. This circuit possesses the low power consumption of CMOS circuitry, yet has speeds comparable to low power Schottky TTL circuits. This device is TTL input compatible and can drive up to 15 LS-TTL loads and all inputs are protected from damage due to static discharge by diodes to VCC and ground. It has one active low enable input and direction control. When the DIR input is HIGH, data flows from the A inputs to the B outputs. When DIR is LOW data flows from B to A. This device is intended to interface between TTL and NMOS components and standard CMOS devices. This part is also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs.