Description The ’HC273 and ’HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicon-gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits. Features • Common Clock and Asynchronous Master Reset • Positive Edge Triggering • Buffered Inputs • Fanout (Over Temperature Range) \- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads \- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types \- 2V to 6V Operation \- High Noise Immunity: NIL= 30%, NIH= 30% of VCC at VCC= 5V • HCT Types \- 4.5V to 5.5V Operation \- Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) \- CMOS Input Compatibility, Il ≤1µA at VOL, VOH
The SN74HC259N is a 8-bit Addressable Latch designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers and active-high decoders or demultiplexers. It is multifunctional devices capable of storing single-line data in eight addressable latches and being a 1-of-8 decoder or demultiplexer with active-high outputs. Four distinct modes of operation are selectable by controlling the clear (CLR)\ and enable (G)\ inputs. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch follows the data input, with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G\ should be held high (inactive) while the address lines are changing.
description/ordering information These 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches and being a 1-of-8 decoder or demultiplexer with active-high outputs. • Wide Operating Voltage Range of 2 V to 6 V • High-Current Inverting Outputs Drive Up To 10 LSTTL Loads • Low Power Consumption, 80-µA Max ICC • Typical tpd = 14 ns • ±4-mA Output Drive at 5 V • Low Input Current of 1 µA Max • 8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion With Storage • Asynchronous Parallel Clear • Active-High Decoder • Enable Input Simplifies Expansion • Expandable for n-Bit Applications • Four Distinct Functional Modes