General Description The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individ ual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh, and eighth stages. All outputs have equal source and sink current capabilities and conform to standard “B” series output drive. When the parallel/serial control input is in the logical “0” state, data is serially shifted into the register synchronously with the positive transition of the clock. When the parallel/serial control is in the logical “1” state, data is jammed into each stage of the register asynchronously with the clock. All inputs are protected against static discharge with diodes to VDDand VSS. Features ■Wide supply voltage range: 3.0V to 15V ■High noise immunity: 0.45 VDD(typ.) ■Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS ■5V–10V–15V parametric ratings ■Symmetrical output characteristics ■Maximum input leakage 1 µA at 15V over full temperature range
For rapid fast switching implement this CD4021BEE4 counter shift register by Texas Instruments. This counter shift register has an operating temperature range of -55 °C to 125 °C. This device comes in tube packaging. This device has a typical operating supply voltage of 3.3|5|9|12|15 V. Its minimum operating supply voltage of 3 V, while its maximum is 18 V.
The CD4021BE is a CMOS 8-stage parallel or serial-input/serial output Static Shift Register with common clock and parallel/serial control inputs, a single serial data input and individual parallel "JAM" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In addition to an output form stage 8, "Q" outputs are also available from stages 6 and 7. In the CD4021B serial entry is synchronous with the clock by parallel entry is asynchronous. In both types, entry is controlled by the parallel/serial control input. When parallel/serial control input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the parallel/serial control input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021BE, the clock input of the internal stage is "forced" when asynchronous parallel entry is made.