The 06035A470FAT2A is a surface-mount (SMT) Multilayer Ceramic Capacitor with Ni and Sn plated terminations. The C0G (NP0) is the most popular formulation of the temperature-compensating, EIA Class I ceramic materials. Modern C0G (NP0) formulations contain neodymium, samarium and other rare earth oxides. C0G (NP0) ceramics offer one of the most stable capacitor dielectrics available. Capacitance change with temperature is 0±30ppm/°C which is less than ±0.3% ΔC from -55 to 125°C. Capacitance drift or hysteresis for C0G (NP0) ceramics is negligible at less than ±0.05% versus up to ±2% for films. Typical capacitance change with life is less than ±0.1% for C0G (NP0), one-fifth that shown by most other dielectrics.
The Kemet C series commercial grade multilayer ceramic chip capacitors is Class 1, C0G dielectric material which exhibits no change in capacitance with respect to time and voltage. There will be negligible change in capacitance with reference to ambient temperature. Standard end terminations use a nickel barrier layer and a matte tin finish to provide excellent soldering ability for customers. Typical applications include timing, tuning, circuits requiring low loss, circuits with pulse, high current, decoupling, bypass, filtering, transient voltage suppression and energy storage. MLCCs are monolithic devices that consist of laminated layers of specially formulated, ceramic dielectric materials interspersed with a metal electrode system. The layered formation is then fired at high temperature to produce a sintered and volumetrically efficient capacitance device. A conductive termination barrier system is integrated on the exposed ends of the chip to complete the connection.
The 06035A470KAT2A is a surface-mount (SMT) Multilayer Ceramic Capacitor with Ni and Sn plated terminations. The C0G (NP0) is the most popular formulation of the temperature-compensating, EIA Class I ceramic materials. Modern C0G (NP0) formulations contain neodymium, samarium and other rare earth oxides. C0G (NP0) ceramics offer one of the most stable capacitor dielectrics available. Capacitance change with temperature is 0±30ppm/°C which is less than ±0.3% ΔC from -55 to 125°C. Capacitance drift or hysteresis for C0G (NP0) ceramics is negligible at less than ±0.05% versus up to ±2% for films. Typical capacitance change with life is less than ±0.1% for C0G (NP0), one-fifth that shown by most other dielectrics.