The 74HC573D is an octal transparent D Latch pin compatible with low-power Schottky TTL (LSTTL). It features separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A LE input and an OE\ input are common to all latches. When LE is high, data at the Dn inputs enter the latches. In this condition, the latch is transparent, i.e. a latch output changes state each time its corresponding D input changes. When LE is low the latches store the information that was present at the D-inputs a set-up time preceding the high-to-low transition of LE. When OE\ is low, the contents of the 8 latches are available at the outputs. When OE\ is high, the outputs go to the high-impedance OFF-state. Operation of the OE\ input does not affect the state of the latch.
The 74HC573D is a high speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC573D has octal D-type transparent latches featuring separate D-type inputs for each latch and 3 state true outputs for bus oriented applications. A latch enable input and an output enable input are common to all latches.
The MM74HC573WM is a 3-state high speed octal D Latch utilizes advanced silicon-gate P-well CMOS technology. It possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-state feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. When the LE input is high, the Q outputs will follow the D inputs. When the LE goes low, data at the D inputs will be retained at the outputs until LE returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function and pinout compatible with the standard 74LS logic family.