The CD74HCT125M96 is a high speed CMOS logic Quad Buffer with 3-state outputs. It contains 4 independent 3-state buffers, each having its own output enable input, which when HIGH puts the output in the high impedance state.

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Separate output enable inputs

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Balanced propagation delay and transition times

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Significant power reduction compared to LSTTL logic Ics

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Standard outputs - 10 LSTTL loads

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Bus driver outputs - 15 LSTTL loads

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CMOS input compatibility, Il

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Direct LSTTL input logic compatibility, VIL = 0.8V maximum, VIH = 2V minimum

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Green product and no Sb/Br

Operating Voltage Range of 4.5 V to 5.5 V High-Current Outputs Drive Up To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 12 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible High-Current 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

The 74HCT125D is a Quad Buffer/Line Driver with 3-state output controlled by the output enable inputs (nOE). A high on nOE causes the outputs to assume a high impedance off-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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TTL Input level

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±1µA Input leakage current

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±10µA Off-state output current

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160µA Supply current

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Complies with JEDEC standard number 7A