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LT3045EDD LDO Voltage Regulators: Datasheet, Pinout, Specification [FAQ]

Author: Irene
Date: 13 May 2022
 129
LT3045EDD Pinout

Product Overview

The LT®3045-EP is a high performance low dropout linear regulator featuring LTC’s ultralow noise and ultrahigh PSRR architecture for powering noise sensitive applications. Designed as a precision current reference followed by a high performance voltage buffer, the LT3045-EP can be easily paralleled to further reduce noise, increase output current and spread heat on the PCB .

 

The device supplies 500mA at a typical 260mV dropout voltage. Operating quiescent current is nominally 2.2mA and drops to <<1µA in shutdown. The LT3045-EP’s wide output voltage range (0V to 15V) while maintaining unity- gain operation provides virtually constant output noise, PSRR, bandwidth and load regulation, independent of the programmed output voltage. Additionally, the regulator features programmable current limit, fast start-up capa- bility and programmable power good to indicate output voltage regulation.

 

The LT3045-EP is stable with a minimum 10µF ceramic output capacitor. Built-in protection includes reverse- battery protection, reverse-current protection, internal current limit with foldback and thermal limit with hysteresis. The LT3045-EP is available in thermally enhanced 12- Lead MSOP package. Additional application and technical information can be found in LT3045 data sheet.

 

This blog will introduce LT3045EDD systematically from its features, pinout to its specifications, applications, also including LT3045EDD datasheet and so much more.

 

Catalog

Product Overview

LT3045EDD Features

LT3045EDD Pinout

Enhanced Product Features

LT3045EDD Applications

Order Information

Electrical Characteristics

Pin Functions

LT3045EDD Block Diagram

LT3045EDD Package

LT3045EDD Specification

LT3045EDD Manufacturer

LT3045EDD Datasheet

Using Warnings

LT3045EDD FAQ

 

LT3045EDD Features

■Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz)

■Ultralow Spot Noise: 2nV/√Ňz at 10kHz

■Ultrahigh PSRR: 76dB at 1MHz

■Output Current: 500mA

■Wide Input Voltage Range: 1.8V to 20V

■Single Capacitor Improves Noise and PSRR

■100µA SET Pin Current: ±1% Initial Accuracy

■Single Resistor Programs Output Voltage

■High Bandwidth: 1MHz

■Programmable Current Limit

■Low Dropout Voltage: 260mV

■Output Voltage Range: 0V to 15V

■Programmable Power Good 

■Fast Start-Up Capability

■Precision Enable/UVLO

■Parallelable for Lower Noise and Higher Current

■Internal Current Limit with Foldback 

■Minimum Output Capacitor: 10µF Ceramic

■Reverse-Battery and Reverse-Current Protection

■12-Lead MSOP Package

 

LT3045EDD Pinout

The following figure is the diagram of LT3045EDD pinout.

 

LT3045EDD Pinout

LT3045EDD Pinout

 

Enhanced Product Features

■Supports Defense and Aerospace Applications (AQEC Standard)

■Military Temperature Range (–55°C to 150°C)

■Controlled Manufacturing Baseline

■One Assembly/Test Site

■One Fabrication Site

■Product Change Notification

■Qualification Data Available on Request

 

LT3045EDD Applications

■RF Power Supplies: PLLsVCOs, Mixers, LNAs, PAs

■Very Low Noise Instrumentation

■High Speed/High Precision Data Converters

■Medical Applications:  Imaging, Diagnostics

■Precision Power Supplies

■Post-Regulator for Switching Supplies

 

Order Information

LEAD FREE FINISH

PART MARKING

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LT3045HMSE#Z-EP

3045EP

12-Lead Plastic MSOP

–55°C to 150°C

 

Electrical Characteristics

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input Voltage Range

 

l

2

 

20

V

Minimum IN Pin Voltage

ILOAD = 500mA, VIN UVLO Rising

l

1.78 2

V

(Note 2)

VIN UVLO Hysteresis

 

75

mV

Output Voltage Range

VIN > VOUT

l

0

 

15

V

SET Pin Current (ISET)

VIN = 2V, ILOAD = 1mA, VOUT = 1.3V

 

99

100

101

µA

98

100

102

µA

2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 500mA (Note 3)

l

Fast Start-Up Set Pin Current

VPGFB = 289mV, VIN = 2.8V, VSET = 1.3V

 

2

mA

Output Offset Voltage

VIN = 2V, ILOAD = 1mA, VOUT = 1.3V

 

–1

 

1

mV

VOS (VOUT – VSET)

(Note 4)

2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 500mA (Note 3)

l

–2

 

2

mV

Line Regulation: ∆ISET

Line Regulation: ∆VOS

VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V

VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V (Note 4)

l l

 

0.5

0.5

±2

±3

nA/V µV/V

 

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: The EN/UV pin threshold must be met to ensure device operation. Note 3: Maximum junction temperature limits operating conditions. The regulated output voltage specification does not apply for all possible

combinations of input voltage and output current, especially due to the

internal current limit foldback which starts to decrease current limit at VIN – VOUT > 12V. If operating at maximum output current, limit the input voltage range. If operating at the maximum input voltage, limit the output current range.

Note 4: OUTS ties directly to OUT.

Note 5: Dropout voltage is the minimum input-to-output differential voltage  needed to maintain regulation at a specified output current. The dropout voltage is measured when output is 1% out of regulation. This definition results in a higher dropout voltage compared to hard dropout

— which is measured when VIN = VOUT(NOMINAL). For lower output voltages, below 1.5V, dropout voltage is limited by the minimum input voltage specification. Please consult the LT3045 Typical Performance Characteristics for curves of dropout voltage as a function of output load current and temperature measured in a typical application circuit.

Note 6: GND pin current is tested with VIN = VOUT(NOMINAL) and a current source load. Therefore, the device is tested while operating in dropout. This is the worst-case  GND pin current. GND pin current decreases at higher input voltages. Note that GND pin current does not include SET pin or ILIM pin current but Quiescent current does include them.

Note 7: SET and OUTS pins are clamped using diodes and two 25Ω series resistors. For less than 5ms transients, this clamp circuitry can carry more than the rated current. Refer to LT3045 Applications Information for more information.

Note 8: Adding a capacitor across the SET pin resistor decreases output voltage noise. Adding this capacitor bypasses the SET pin resistor’s thermal noise as well as the reference current’s noise. The output noise then equals the error amplifier noise. Use of a SET pin bypass capacitor also increases start-up time.

Note 9: The LT3045-EP is tested and specified under pulsed load conditions such that TJ ≈ TA. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C.

Note 10: Parasitic diodes exist internally between the ILIM, PG, PGFB, SET, OUTS, and OUT pins and the GND pin. Do not drive these pins more than 0.3V below the GND pin during a fault condition. These pins must remain at a voltage more positive than GND during normal operation.

Note 11: The current limit programming scale factor is specified while the internal backup current limit is not active. Note that the internal current limit has foldback protection for VIN – VOUT differentials greater than 12V. Note 12: The internal back-up current limit circuitry incorporates foldback protection that decreases current limit for VIN – VOUT > 12V. Some level of output current is provided at all VIN – VOUT differential voltages. Consult the LT3045 Typical Performance Characteristics graph for current limit vs VIN – VOUT.

Note 13: For output voltages less than 1V, the LT3045-EP requires a 10µA minimum load current for stability.

Note 14: Maximum OUT-to-OUTS differential is guaranteed by design.

 

Pin Functions

IN (Pins 1, 2, 3): Input. These pins supply power to the regulator. The LT3045-EP requires a bypass capacitor at the  IN  pin. In general, a battery’s output impedance rises with frequency, so include a bypass capacitor in battery- powered applications. While a 4.7µF input bypass capacitor generally suffices, applications with large load transients  may require higher input capacitance to prevent input supply droop. Consult the LT3045 Applications Informa- tion section on the proper use of an input capacitor and its effect on circuit performance, in particular PSRR. The LT3045-EP withstands reverse voltages on IN with respect to GND, OUTS and OUT. In the case of a reversed input, which occurs if a battery is plugged-in backwards, the LT3045-EP acts as if a diode is in series with its input. Hence, no reverse current flows into the LT3045-EP and no negative voltage appears at the load. The device protects itself and the load.

EN/UV (Pin 4): Enable/UVLO. Pulling the LT3045-EP’s EN/ UV  pin low places the part in shutdown. Quiescent cur- rent in shutdown drops to less than 1µA and the output voltage turns off. Alternatively, the EN/UV pin can set an input supply undervoltage lockout (UVLO) threshold us- ing a resistor divider between IN, EN/UV and GND. The LT3045-EP typically turns on when the EN/UV voltage exceeds 1.24V on its rising edge, with a 130mV hysteresis on its falling edge. The EN/UV pin can be driven above the input voltage and maintain proper functionality. If unused, tie EN/UV to IN. Do not float the EN/UV pin.

PG (Pin 5): Power Good. PG is an open-collector flag that indicates output voltage regulation. PG pulls low if PGFB is below 300mV. If the power good functionality is not needed, float the PG pin. A parasitic substrate diode exists between PG and GND pins of the LT3045-EP; do not drive PG more than 0.3V below GND during normal operation or during a fault condition.

ILIM (Pin 6): Current Limit Programming Pin. Connecting a resistor between ILIM and GND programs the current limit. For best accuracy, Kelvin connect this resistor directly to the LT3045-EP’s GND pin. The programming scale factor is nominally 150mA•kΩ. The ILIM pin sources current proportional (1:500) to output current; therefore, it also serves as a current monitoring pin with a 0V to 300mV range. If the programmable current limit functionality is not needed, tie ILIM to GND. A parasitic substrate diode exists between ILIM and GND pins of the LT3045-EP; do not drive ILIM more than 0.3V below GND during normal operation or during a fault condition.

PGFB (Pin 7): Power Good Feedback. The PG pin pulls high if PGFB increases beyond 300mV on its rising edge, with 7mV hysteresis on its falling edge. Connecting an external resistor divider between OUT, PGFB and GND sets the programmable power good threshold with the

following transfer function: 0.3V • (1 + RPG2/RPG1). As discussed in the LT3045 Applications Information section, PGFB also activates the fast start-up circuitry. Tie PGFB to IN if power good and fast start-up functionalities are not needed, and if reverse input protection is additionally

required, tie the anode of a 1N4148 diode to IN and its cathode to PGFB. See the LT3045 Typical Applications sec- tion for details. A parasitic substrate diode exists between PGFB and GND pins of the LT3045-EP; do not drive PGFB more than 0.3V below GND during normal operation or during a fault condition.

SET (Pin 8): SET. This pin is the inverting input of the er- ror amplifier and the regulation set-point for the LT3045- EP. SET sources a precision 100µA current that flows through an external resistor connected between SET and GND. The LT3045-EP’s output voltage is determined by

VSET = ISET • RSET. Output voltage range is from zero to 15V. Adding a capacitor from SET to GND improves noise, PSRR and transient response at the expense of increased start-up time. For optimum load regulation,  Kelvin con- nect the ground side of the SET pin resistor directly to the load. A parasitic substrate diode exists between SET and GND pins of the LT3045-EP; do not drive SET more than 0.3V below GND during normal operation or during a fault condition.

GND (Pin 9, Exposed Pad Pin 13): Ground. The exposed backside is an electrical connection to GND. To ensure proper electrical and thermal performance, solder the exposed backside to the PCB ground and tie it directly to the GND pin.

OUTS (Pin 10): Output Sense. This pin is the noninvert- ing input to the error amplifier. For optimal transient performance and load regulation, Kelvin connect OUTS directly to the output capacitor and the load. Also, tie the GND connections of the output capacitor and the SET pin capacitor directly together. A parasitic substrate diode ex- ists between OUTS and GND pins of the LT3045-EP; do not drive OUTS more than 0.3V below GND during normal operation or during a fault condition.

OUT (Pins 11, 12): Output. This pin supplies power to the load. For stability, use a minimum 10µF output capacitor with an ESR below 20mΩ and an ESL below 2nH. Large load transients  require larger output capacitance to limit peak voltage transients. Refer to the LT3045 Applications Information section for more information on output ca- pacitance. A parasitic substrate diode exists between OUT and GND pins of the LT3045-EP; do not drive OUT more than 0.3V below GND during normal operation or during a fault condition.

 

LT3045EDD Block Diagram

The following figure shows the block diagram of LT3045EDD.

 

LT3045EDD Block Diagram

LT3045EDD Block Diagram

 

LT3045EDD Package

The following diagram shows the LT3045EDD package.

 

LT3045EDD Package

LT3045EDD Package

 

NOTE:

1.DIMENSIONS IN MILLIMETER/(INCH)

2.DRAWING NOT TO SCALE

3.DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4.DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5.LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6.EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

 

LT3045EDD Specification

Product Attribute Attribute Value
Manufacturer: Analog Devices Inc.
Product Category: LDO Voltage Regulators
Mounting Style: SMD/SMT
Package / Case: DFN-10
Output Voltage: 0 V to 15 V
Output Current: 500 mA
Number of Outputs: 1 Output
Polarity: Positive
Quiescent Current: 2.2 mA
Input Voltage, Min: 1.8 V
Input Voltage, Max: 20 V
PSRR / Ripple Rejection - Typ: 76 dB
Output Type: Adjustable
Minimum Operating Temperature: - 40 C
Maximum Operating Temperature: + 125 C
Dropout Voltage: 260 mV
Series: LT3045
Packaging: Tube
Brand: Analog Devices
Development Kit: DC2491A
Dropout Voltage - Max: 350 mV
Line Regulation: 0.5 uV/V
Load Regulation: 0.1 mV
Operating Supply Current: 2.4 mA
Output Voltage Range: 0 V to 15 V

 

LT3045EDD Manufacturer

Analog Devices (NASDAQ: ADI) is a world leader in the design, manufacture, and marketing of a broad portfolio of high performance analog, mixed-signal, and digital signal processing (DSP) integrated circuits (ICs) used in virtually all types of electronic equipment.

 

LT3045EDD Datasheet

You can download LT3045EDD datasheet from the link given below:

LT3045EDD Datasheet

 

Using Warnings

Note: Please check their parameters and pin configuration before replacing them in your circuit.

 

LT3045EDD FAQ

What is LDO in voltage regulator?

An LDO regulator is a linear regulator that can operate at a very low potential difference between the input and output voltage. A linear regulator is a type of power supply IC that can output a steady voltage from an input voltage and is used in a variety of electronic devices.

 

How does LDO regulator work?

A low-dropout regulator's (LDO) nature is to regulate a voltage by turning excess power into heat, making this integrated circuit a good fit for low-power or small VIN-to-VOUT differential applications.

 

What is the difference between LDO and voltage regulator?

There are two types of linear regulators: standard linear regulators and low dropout linear regulators (LDOs). The difference between the two is in the pass element and the amount of headroom, or dropout voltage, required to maintain a regulated output voltage.

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