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HEF4001B NOR Gate: CAD Models, Datasheet, Features [FAQ]

Author: Lydia
Date: 14 Jan 2023
 146

Ordering & Quality

Photo Mfr. Part # Company Description Package PDF Qty Pricing
(USD)
HEF4001BP-652 HEF4001BP-652 Company:Rochester Electronics, LLC Remark:NOR GATE Package:14-DIP
DataSheet
In Stock:On Order
Buy
Price:
782+: $0.32000
Buy
HEF4001BT-Q100J HEF4001BT-Q100J Company:Nexperia USA Inc. Remark:NOR Gate IC 4 Channel 14-SO Package:14-SOIC (0.154", 3.90mm Width)
DataSheet
In Stock:2369
Buy
Price:
1+: $0.57000
10+: $0.48900
25+: $0.45680
100+: $0.36540
250+: $0.33928
500+: $0.28706
1000+: $0.22183
2500+: $0.20225
5000+: $0.18920
12500+: $0.18465
Buy

Catalog

Product Overview

HEF4001B CAD Models

HEF4001B Pin Configuration

HEF4001B Functional Diagram

HEF4001B Logic Diagram

HEF4001B Features

HEF4001B Datasheet

HEF4001B Specifications

HEF4001B Manufacturer

Using Warning

HEF4001B FAQ

 

Product Overview

The HEF4001B is a quad 2-input NOR gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance.

 

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

 

HEF4001B CAD Models

HEF4001B PCB Symbol

Figure: HEF4001B PCB Symbol

 

 

HEF4001B Footprint 

Figure: HEF4001B Footprint

 

 

 HEF4001B 3D Models

Figure: HEF4001B 3D Models

 

HEF4001B Pin Configuration

HEF4001B Pin Configuration

Figure: HEF4001B Pin Configuration

 

HEF4001B Functional Diagram

HEF4001B Functional Diagram

Figure: HEF4001B Functional Diagram

 

HEF4001B Logic Diagram

HEF4001B Logic Diagram

Figure: HEF4001B Logic Diagram

 

HEF4001B Features

  • Fully static operation
  • 5 V, 10 V, and 15 V parametric ratings
  • Standardized symmetrical output characteristics
  • Specified from -40 ℃ to +125 ℃
  • Complies with JEDEC standard JESD 13-B
  • Inputs and outputs are protected against electrostatic effects

 

HEF4001B Datasheet

You can download the datasheet from the link given below:

HEF4001B Datasheet

 

HEF4001B Specifications

Product Attribute Attribute Value
Manufacturer: NXP
Product Category: Logic Gates
Product: Single-Function Gate
Logic Function: NOR
Logic Family: HEF4000
Number of Gates: 4 Gate
Number of Input Lines: 2 Input
Number of Output Lines: 1 Output
High Level Output Current: - 3.6 mA
Low Level Output Current: 3.6 mA
Propagation Delay Time: 120 ns
Supply Voltage - Max: 15 V
Supply Voltage - Min: 3 V
Minimum Operating Temperature: - 40
Maximum Operating Temperature: + 85
Mounting Style: Through Hole
Package/Case: PDIP-14
Packaging: Bulk
Brand: NXP Semiconductors
Function: NOR
Height: 3.2 mm
Length: 19.5 mm
Logic Type: CMOS
Operating Supply Voltage: 3.3 V, 5 V, 9 V, 12 V
Product Type: Logic Gates
Subcategory: Logic ICs
Width: 6.48 mm
Unit Weight: 1.620 g

 

HEF4001B Manufacturer

NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the secure connected vehicle, end-to-end security and privacy and smart connected solutions markets.

 

Using Warning

Note: Please check their parameters and pin configuration before replacing them in your circuit.

 

HEF4001B FAQ

Where is NOR gate used?

A few of the NOR Gate applications are explained as below: These are used in combinational circuits such as multipliers, multiplexers, half and full adders, and in ripple-carry adders. Also used in sequential circuits and in shift registers also.

 

Is NOR gate opposite of OR gate?

A NOR gate (sometimes referred to by its extended name, Negated OR gate) is a digital logic gate with two or more inputs and one output with behavior that is the opposite of an OR gate.

 

What is the difference between NAND and NOR gate?

A NAND gate is a universal logic gate which performs the negated logical multiplication. A NOR gate is a universal logic gate which performs the negated logical addition. NAND gate can be implemented by using an AND gate followed by a NOT gate. NOR gate can be implemented by using an OR gate followed by a NOT gate.

 

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