Catalog
General Description
The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Features and Benefits
- Complies with JEDEC standard JESD7A
- Inputlevels:
- For 74HC10: CMOS level
- For 74HCT10: TTL level
- Complies with JEDEC standard no.7A
- ESD protection:
- HBM JESD22-A114F exceeds 2000V
- MM JESD22-A115-A exceeds 200V
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125°C
Type number
|
Package
|
Temperature range
|
Name
|
Description
|
Version
|
74HC10D
|
-40 °C to +125 °C
|
SO14
|
plastic small outline package; 14 leads; body width 3.9 mm
|
SOT108-1
|
74HCT10D
|
74HC10PW
|
-40 °C to +125 °C
|
TSSOP14
|
plastic thin shrink small outline package; 14 leads; body width 4.4 mm
|
SOT402-1
|
74HCT10PW
|
Functional Diagram
Logic Symbol
IEC Logic Symbol
Logic Diagram for One Gate
Pin Configuration SOT108-1 (SO14)
Pin Configuration SOT402-1 (TSSOP14)
Pin Description
Symbol
|
Pin
|
Description
|
1A, 2A, 3A
|
1, 3, 9
|
data input
|
1B, 2B, 3B
|
2, 4, 10
|
data input
|
GND
|
7
|
ground (0 V)
|
1C, 2C, 3C
|
13, 5, 11
|
data input
|
1Y, 2Y, 3Y
|
12, 6, 8
|
data output
|
VCC
|
14
|
supply voltage
|
Functional Description
H = HIGH voltage level; L = LOW voltage level; X = don’t care
Input
|
Output
|
nA
|
nB
|
nC
|
nY
|
L
|
X
|
X
|
H
|
X
|
L
|
X
|
H
|
X
|
X
|
L
|
H
|
H
|
H
|
H
|
L
|
Limiting Values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
|
Parameter
|
Conditions
|
Min
|
Max
|
Unit
|
VCC
|
supply voltage
|
|
-0.5
|
+7
|
V
|
IIK
|
input clamping current
|
VI < -0.5 V or VI > VCC + 0.5 V [1]
|
-
|
±20
|
mA
|
IOK
|
output clamping current
|
VO < -0.5 V or VO > VCC + 0.5 V [1]
|
-
|
±20
|
mA
|
IO
|
output current
|
-0.5 V < VO < VCC + 0.5 V
|
-
|
±25
|
mA
|
ICC
|
supply current
|
|
-
|
50
|
mA
|
IGND
|
ground current
|
|
-50
|
-
|
mA
|
Tstg
|
storage temperature
|
|
-65
|
+150
|
°C
|
Ptot
|
total power dissipation
|
[2]
|
-
|
500
|
mW
|
[1]The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.
Recommended Operating Conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
|
Parameter
|
Conditions
|
74HC10
|
74HCT10
|
Unit
|
Min
|
Typ
|
Max
|
Min
|
Typ
|
Max
|
VCC
|
supply voltage
|
|
2.0
|
5.0
|
6.0
|
4.5
|
5.0
|
5.5
|
V
|
VI
|
input voltage
|
|
0
|
-
|
VCC
|
0
|
-
|
VCC
|
V
|
VO
|
output voltage
|
|
0
|
-
|
VCC
|
0
|
-
|
VCC
|
V
|
Tamb
|
ambient temperature
|
|
-40
|
-
|
+125
|
-40
|
-
|
+125
|
°C
|
Δt/ΔV
|
input transition rise and fall rate
|
VCC = 2.0 V
|
-
|
-
|
625
|
-
|
-
|
-
|
ns/V
|
VCC = 4.5 V
|
-
|
1.67
|
139
|
-
|
1.67
|
139
|
ns/V
|
VCC = 6.0 V
|
-
|
-
|
83
|
-
|
-
|
-
|
ns/V
|
Static Characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
|
Parameter
|
Conditions
|
25 °C
|
-40 °C to +85 °C
|
-40 °C to +125 °C
|
Unit
|
Min
|
Typ
|
Max
|
Min
|
Max
|
Min
|
Max
|
VIH
|
HIGH-level input voltage
|
VCC = 2.0 V
|
1.5
|
1.2
|
-
|
1.5
|
-
|
1.5
|
-
|
V
|
VCC = 4.5 V
|
3.15
|
2.4
|
-
|
3.15
|
-
|
3.15
|
-
|
V
|
VCC = 6.0 V
|
4.2
|
3.2
|
-
|
4.2
|
-
|
4.2
|
-
|
V
|
VIL
|
LOW-level input voltage
|
VCC = 2.0 V
|
-
|
0.8
|
0.5
|
-
|
0.5
|
-
|
0.5
|
V
|
VCC = 4.5 V
|
-
|
2.1
|
1.35
|
-
|
1.35
|
-
|
1.35
|
V
|
VCC = 6.0 V
|
-
|
2.8
|
1.8
|
-
|
1.8
|
-
|
1.8
|
V
|
VOH
|
HIGH-level output voltage
|
VI = VIH or VIL
|
|
|
|
|
|
|
|
|
IO = -20 μA; VCC = 2.0 V
|
1.9
|
2.0
|
-
|
1.9
|
-
|
1.9
|
-
|
V
|
IO = -20 μA; VCC = 4.5 V
|
4.4
|
4.5
|
-
|
4.4
|
-
|
4.4
|
-
|
V
|
IO = -20 μA; VCC = 6.0 V
|
5.9
|
6.0
|
-
|
5.9
|
-
|
5.9
|
-
|
V
|
IO = -4.0 mA; VCC = 4.5 V
|
3.98
|
4.32
|
-
|
3.84
|
-
|
3.7
|
-
|
V
|
IO = -5.2 mA; VCC = 6.0 V
|
5.48
|
5.81
|
-
|
5.34
|
-
|
5.2
|
-
|
V
|
VOL
|
LOW-level output voltage
|
VI = VIH or VIL
|
|
|
|
|
|
|
|
|
IO = 20 μA; VCC = 2.0 V
|
-
|
0
|
0.1
|
-
|
0.1
|
-
|
0.1
|
V
|
IO = 20 μA; VCC = 4.5 V
|
-
|
0
|
0.1
|
-
|
0.1
|
-
|
0.1
|
V
|
IO = 20 μA; VCC = 6.0 V
|
-
|
0
|
0.1
|
-
|
0.1
|
-
|
0.1
|
V
|
IO = 4.0 mA; VCC = 4.5 V
|
-
|
0.15
|
0.26
|
-
|
0.33
|
-
|
0.4
|
V
|
IO = 5.2 mA; VCC = 6.0 V
|
-
|
0.16
|
0.26
|
-
|
0.33
|
-
|
0.4
|
V
|
II
|
input leakage current
|
VI = VCC or GND; VCC = 6.0 V
|
-
|
-
|
±0.1
|
-
|
±1
|
-
|
±1
|
μA
|
ICC
|
supply current
|
VI = VCC or GND; IO = 0 A; VCC = 6.0 V
|
-
|
-
|
2.0
|
-
|
20
|
-
|
40
|
μA
|
CI
|
input capacitance
|
|
-
|
3.5
|
-
|
-
|
-
|
-
|
-
|
pF
|
Dynamic Characteristics
GND = 0 V; CL = 50 pF; for test circuit, see Figure.
Symbol
|
Parameter
|
Conditions
|
25 °C
|
-40 °C to
+85 °C
|
-40 °C to
+125 °C
|
Unit
|
Min
|
Typ
|
Max
|
Max
|
Max
|
tpd
|
propagation delay
|
nA, nB to nY; see Figure [1]
|
|
|
|
|
|
|
VCC = 2.0 V
|
-
|
30
|
95
|
120
|
145
|
ns
|
VCC = 4.5 V
|
-
|
11
|
19
|
24
|
29
|
ns
|
VCC = 5.0 V; CL = 15 pF
|
-
|
9
|
-
|
-
|
-
|
ns
|
VCC = 6.0 V
|
-
|
9
|
16
|
20
|
25
|
ns
|
tt
|
transition time
|
see Figure [2]
|
|
|
|
|
|
|
VCC = 2.0 V
|
-
|
19
|
75
|
95
|
110
|
ns
|
VCC = 4.5 V
|
-
|
7
|
15
|
19
|
22
|
ns
|
VCC = 6.0 V
|
-
|
6
|
13
|
16
|
19
|
ns
|
CPD
|
power dissipation capacitance
|
per package; VI = GND to VCC [3]
|
-
|
12
|
-
|
-
|
-
|
pF
|
[1]tpd is the same as tPHL and tPLH.
[2]tt is the same as tTHL and tTLH.
[3]CPD is used to determine the dynamic power dissipation (PD in μW): PD = CPD x VCC 2 x fi x N + Σ(CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz;
CL = output load capacitance in pF; VCC = supply voltage in V;
N = number of inputs switching; Σ(CL x VCC 2 x fo) = sum of outputs.
74HC10 Datasheet
You can download the datasheet of 74HC10 from the link given below:
74HC10 Datasheet
74HC10 FAQ
As with the AND function seen previously, the NAND function can also have any number of individual inputs and commercial available NAND Gate IC's are available in standard 2, 3, or 4 input types. If additional inputs are required, then the standard NAND gates can be cascaded together to provide more inputs for example.
The 3-input NAND Gate
Unlike the 2-input NAND gate, the 3-input NAND gate has three inputs. The Boolean expression of the logic NAND gate is defined as the binary operation dot(.). The NAND gate can be cascaded together to form any number of individual inputs. There are 23=8 possible combinations of inputs.
What is function of a NAND gate?
In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces an output which is false only if all its inputs are true; thus its output is complement to that of an AND gate.
What is NAND truth table?
The NAND gate is a combination of an AND gate and NOT gate. They are connected in cascade form. It is also called Negated And gate. The NAND gate provides the false or low output only when their outputs is high or true.
What is a NAND?
NAND Flash is a type of non-volatile storage technology that does not require power to retain data. An everyday example would be a mobile phone, with the NAND Flash (or the memory chip as it's sometimes called) being where data files such as photos, videos and music are stored on a microSD card.