Product Overview
Kynix Part #: | KY32-MCF52230CAL60 |
Manufacturer Part#: | MCF52230CAL60 |
Product Category: | Embedded - Microcontrollers |
Stock: | Yes |
Manufacturer: | Freescale Semiconductor - NXP |
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Description: | IC MCU 32BIT 128KB FLASH 112LQFP |
Datasheet: | MCF52230CAL60 Datasheet |
Package: | 112-LQFP |
Quantity: | 622 PCS |
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Product Attributes
Manufacturer: | Freescale Semiconductor - NXP |
Product Category: | Embedded - Microcontrollers |
Status: | Active |
Series: | MCF5223x |
ADC Channels: | 8 |
ADC Resolution: | 12 bit |
Address Bus Width: | 0.0 |
Bit Size: | 32 |
Core Size: | 32-Bit |
Core Processor: | Coldfire V2 |
Core Architecture: | ColdFire |
CPU Family: | COLDFIRE |
Connectivity: | Ethernet, I²C, SPI, UART/USART |
Clock Frequency-Max: | 60.0 MHz |
China RoHS Compliant: | Yes |
Device Core: | ColdFire |
DAC Channels: | No |
DMA Channels: | Yes |
Data Converters: | A/D 8x12b |
Data Bus Width: | 32 bit |
EEPROM Size: | - |
EU RoHS Compliant: | Yes |
External Data Bus Width: | 0.0 |
Frequency: | 60 MHz |
Family Name: | MCF5223x |
Interface Type : | I2C, QSPI, UART |
Instruction Set Architecture: | RISC |
JESD-30 Code: | S-PQFP-G112 |
JESD-609 Code: | e3 |
Length: | 20.0 mm |
Lead Finish: | Matte Tin |
Lead Shape: | Gull-wing |
Mounting Type: | Surface Mount |
Mounting-Style: | SMD/SMT |
Maximum CPU Frequency: | 60 MHz |
Maximum Clock Frequency: | 60 MHz |
Maximum Expanded Memory Size: | 4 GB |
Number of Bits: | 32 |
Number of I/Os: | 73 |
Number of Pins: | 112 |
Number of ADCs: | Single |
Number of Timers | 10 |
Number of I/O Lines: | 73.0 |
Number of Terminals: | 112 |
Number of SPI Channels: | 1 |
Number of I2C Channels: | 1 |
Number of UART Channels: | 3 |
Number of Ethernet Channels: | 1 |
Number of Programmable I/Os: | 56 |
On-Chip ADC: | 8-chx12-bit |
Oscillator Type: | Internal |
Operating Temperature-Min: | -40.0°C |
Operating Temperature-Max: | 85.0°C |
PWM: | 1 |
Peripherals: | DMA, LVD, POR, PWM, WDT |
Pin Count: | 112 |
PCB changed: | 112 |
Product Type: | 32-bit Microcontrollers - MCU |
Power Supplies: | 3.3 |
Package/Case: | 112-LQFP |
Package Style: | FLATPACK, LOW PROFILE |
Package Shape: | SQUARE |
Package Code: | LFQFP |
Package Body Material: | PLASTIC/EPOXY |
Package Equivalence Code: | QFP112,.87SQ |
Peak Reflow Temperature: | 260°C |
Programmability: | Yes |
Program Memory Size: | 128 KB (128K x 16) |
Program Memory Type: | Flash |
RAM Size: | 32 K x 16 |
RAM (bytes): | 32768.0 |
ROM (words): | 131072 |
ROM Programmability: | FLASH |
Speed: | 60.0 MHz |
Sub Category: | Microcontrollers |
Surface Mount: | Yes |
Seated Height-Max: | 1.6 mm |
Supply Voltage-Nom: | 3.3 V |
Supply Voltage-Min: | 3.0 V |
Supply Voltage-Max: | 3.6 V |
Supplier Device Package: | 112-LQFP (20x20) |
Tradename: | ColdFire |
Technology: | CMOS |
Terminal Form: | GULL WING |
Terminal Pitch: | 0.65 mm |
Terminal Finish: | Matte Tin (Sn) |
Terminal Position: | QUAD |
Temperature Grade: | INDUSTRIAL |
Time@Peak Reflow Temperature-Max: | 40 s |
Unit Weight: | 0.045066 oz |
Width: | 20.0 mm |
Watchdog: | 1 |
Product Features
• Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 60 MHz processor core frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions for improved bit processing (ISA_A+)
— Enhanced Multiply-Accumulate (EMAC) unit with 32-bit accumulator to support 16 x 16 → 32 or 32 x 32 → 32 operations
— Cryptography Acceleration Unit (CAU)
– Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions
– FIPS-140 compliant random number generator
— Support for DES, 3DES, AES, MD5, and SHA-1 algorithms
— Illegal instruction decode that allows for 68K emulation support
• System debug support
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can be configured into a 1- or 2-level trigger
• On-chip memories
— Up to 32 Kbytes of dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply support
— Up to 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses
• Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
• Fast Ethernet Controller (FEC)
— 10/100 BaseT/TX capability, half duplex or full duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
— Memory-based flexible descriptor rings
• On-chip Ethernet Transceiver (EPHY)
— Digital adaptive equalization
— Supports auto-negotiation
— Baseline wander correction
— Full-/Half-duplex support in all modes
— Loopback modes
— Supports MDIO preamble suppression
— Jumbo packet
• FlexCAN 2.0B module
— Based on and includes all existing features of the Freescale TouCAN module
— Full implementation of the CAN protocol specification version 2.0B
– Standard Data and Remote Frames (up to 109 bits long)
– Extended Data and Remote Frames (up to 127 bits long)
– 0–8 bytes data length
– Programmable bit rate up to 1 Mbit/sec
— Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length each, configurable as Rx or Tx, all supporting standard and extended messages
— Unused Message Buffer space can be used as general purpose RAM space
— Listen only mode capability
— Content-related addressing
— No read/write semaphores required
— Three programmable mask registers: global for MBs 0-13, special for MB14, and special for MB15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
— Time stamp based on 16-bit free-running timer
— Global network time, synchronized by a specific message
— Maskable interrupts
• Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
— Up to 2 stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
• I2C module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master and slave modes support multiple masters
— Automatic interrupt generation with programmable level
• Queued serial peripheral interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available
— Master mode operation only
— Programmable bit rates up to half the CPU clock frequency
— Up to 16 pre-programmed transfers
• Fast analog-to-digital converter (ADC)
— Eight analog input channels
— 12-bit resolution
— Minimum 1.125 ms conversion time
— Simultaneous sampling of two channels for motor control applications
— Single-scan or continuous operation
— Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit
— Unused analog channels can be used as digital I/O
• Four 32-bit DMA timers
— 17-ns resolution at 60 MHz
— Programmable sources for clock input, including an external clock option
— Programmable prescaler
— Input capture capability with programmable trigger edge on input pin
— Output compare with programmable mode for the output pin
— Free run and restart modes
— Maskable interrupts on input capture or output compare
— DMA trigger capability on input capture or output compare
• Four-channel general purpose timers
— 16-bit architecture
— Programmable prescaler
— Output pulse widths variable from microseconds to seconds
— Single 16-bit input pulse accumulator
— Toggle-on-overflow feature for pulse-width modulator (PWM) generation
— One dual-mode pulse accumulation channel
• Pulse-width modulation timer
— Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution
— Programmable period and duty cycle
— Programmable enable/disable for each channel
— Software selectable polarity for each channel
— Period and duty cycle are double buffered. Change takes effect when the end of the current period is reached (PWM counter reaches zero) or when the channel is disabled.
— Programmable center or left aligned outputs on individual channels
— Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
— Emergency shutdown
• Real-Time Clock (RTC)
— Maintains system time-of-day clock
— Provides stopwatch and alarm interrupt functions
• Two periodic interrupt timers (PITs)
— 16-bit counter
— Selectable as free running or count down
• Software watchdog timer
— 32-bit counter
— Low power mode support
• Clock Generation Features
— Crystal input
— On-chip PLL
— Provides clock for integrated EPHY
• Dual Interrupt Controllers (INTC0/INTC1)
— Support for multiple interrupt sources organized as follows:
– Fully-programmable interrupt sources for each peripheral
– 7 fixed-level interrupt sources
– Seven external interrupt signals
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low power modes
• DMA controller
— Four fully programmable channels
— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4 x 32-bit) burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)
• Reset
— Separate reset in and reset out signals
— Seven sources of reset:
– Power-on reset (POR)
– External
– Software
– Watchdog
– Loss of clock
– Loss of lock
– Low-voltage detection (LVD)
— Status flag indication of source of last reset
• Chip integration module (CIM)
— System configuration during reset
— Selects one of three clock modes
— Configures output pad drive strength
— Unique part identification number and part revision number
• General purpose I/O interface
— Up to 56 bits of general purpose I/O
— Bit manipulation supported via set/clear functions
— Programmable drive strengths
— Unused peripheral pins may be used as extra GPIO
• JTAG support for system level board testing
Applications
There is no relevant information available for this part yet.
Advantages and Disadvantages
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ECCN / UNSPSC
ECCN | 3A991.A.2 |
HTSN: | 8542310001 |
SCHEDULE B: | 8542310000 |
Environmental & Export Classifications
Moisture Sensitivity Level (MSL) | 3(168 Hours) |
Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
Product Compliance
USHTS: | 8542310001 |
CAHTS: | 8542310000 |
CNHTS: | 8542319000 |
JPHTS: | 8542310324 |
KRHTS: | 8542311000 |
MXHTS: | 85423199 |
TARIC: | 8542319000 |
REACH SVHC: | No SVHC |
Halogen Free: | Halogen Free |
Radiation Hardening: | No |
Documents & Media
Product Manufacturer
NXP Semiconductor enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets. Built on more than 60 years of combined experience and expertise, the company has 45,000 employees in more than 35 countries.
Product Range
ARM ® PROCESSORS | ANALOG | POWER ARCHITECTURE ®PROCESSORS |
MEDIA AND AUDIO | RF | IDENTIFICATION & SECURITY |
Sensors | Wireless | Automotive Products |
Distributors
Distributors | Stock | Manufacturers | Descriptions |
Kynix | 622 | Freescale Semiconductor - NXP | IC MCU 32BIT 128KB FLASH 112LQFP |
DigiKey | 0 | NXP USA Inc. | IC MCU 32BIT 128KB FLASH 112LQFP |
Mouser | 0 | NXP Semiconductors | 32-bit Microcontrollers - MCU KIRIN2E EPP |
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