Product Overview
Kynix Part #: | KY32-MC56F8002VWL |
Manufacturer Part#: | MC56F8002VWL |
Product Category: | Embedded - Microcontrollers |
Stock: | Yes |
Manufacturer: | Freescale Semiconductor - NXP |
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Description: | IC MCU 16BIT 12KB FLASH 28SOIC |
Datasheet: | MC56F8002VWL Datasheet |
Package: | 28-SOIC (0.295", 7.50mm Width) |
Quantity: | 1139 PCS |
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Product Attributes
Manufacturer: | Freescale Semiconductor - NXP |
Product Category: | Embedded - Microcontrollers |
Status: | Active |
Series: | 56F8xxx |
ADC Resolution: | 12 bit |
Address Bus Width: | 0.0 |
Bit Size: | 16 |
Core Size: | 16-Bit |
Core Processor: | 56800E |
CPU Family: | 56800E |
Connectivity: | I²C, LINbus, SCI, SPI |
Clock Frequency-Max: | 64.0 MHz |
China RoHS Compliant: | Yes |
Density: | 96 kb |
Device Core: | 56800 E |
Data Converters: | A/D 15x12b |
DAC Channels: | No |
DMA Channels: | Yes |
Data Bus Width: | 16 bit |
EEPROM Size: | - |
EU RoHS Compliant: | Yes |
External Data Bus Width: | 0.0 |
Interface: | I2C, LIN, SCI, SPI |
JESD-30 Code: | R-PDSO-G28 |
JESD-609 Code: | e3 |
Length: | 17.925 mm |
Lead Finish: | Matte Tin |
Mounting Type: | Surface Mount |
Mounting Style: | SMD/SMT |
Maximum Clock Frequency: | 32 MHz |
Number of I/Os: | 9 |
Number of Pins: | 28 |
Number of Timers | 3 |
Number of I/O Lines: | 23 |
Number of Terminals: | 28 |
Number of Programmable I/O: | 40 |
Oscillator Type: | Internal |
Operating Temperature-Min: | -40°C |
Operating Temperature-Max: | 105°C |
Peripherals: | I2C, LVD, POR, PWM, WDT |
Product Type: | DSP - Digital Signal Processors & Controllers |
PWM Channels: | Yes |
Pin Count: | 28 |
Power Supplies: | 3.3 |
Package/Case: | 28-SOIC (0.295", 7.50mm Width) |
Package Style: | SMALL OUTLINE |
Package Shape: | RECTANGULAR |
Package Code: | SOP |
Package Body Material: | PLASTIC/EPOXY |
Package Equivalence Code: | SOP28,.4 |
Peak Reflow Temperature: | 260°C |
Program Memory Size: | 12 KB (6K x 16) |
Program Memory Type: | Flash |
RAM Size: | 1K x 16 |
RAM (bytes): | 2048.0 |
ROM (words): | 12288 |
ROM Programmability: | FLASH |
Speed: | 32.0 MHz |
Sub Category: | Microcontrollers |
Surface Mount: | Yes |
Seated Height-Max: | 2.65 mm |
Supply Voltage-Nom: | 3.3 V |
Supply Voltage-Min: | 1.8 V |
Supply Voltage-Max: | 3.6 V |
Supplier Device Package: | 28-SOIC |
Technology: | CMOS |
Terminal Form: | GULL WING |
Terminal Pitch: | 1.27 mm |
Terminal Finish: | Matte Tin (Sn) |
Terminal Position: | DUAL |
Temperature Grade: | INDUSTRIAL |
Time@Peak Reflow Temperature-Max: | 40 s |
Unit Weight: | 0.026676 oz |
Width: | 7.5 mm |
Product Features
• Efficient 16-bit 56800E family digital signal controller (DSC) engine with dual Harvard architecture
• As many as 32 million instructions per second (MIPS) at 32 MHz core frequency
• 155 basic instructions in conjunction with up to 20 address modes
• Single-cycle 16 ´ 16-bit parallel multiplier-accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• 32-bit arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging
• 1.8 V to 3.6 V operation (power supplies and I/O)
• From power-on-reset: approximately 1.9 V to 3.6 V
• Ambient temperature operating range:
— –40 °C to 125 °C
• Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
• Flash security and protection that prevent unauthorized users from gaining access to the internal flash
• On-chip memory
— 16 KB of program flash for 56F8006 and 12 KB of program flash for 56F8002
— 2 KB of unified data/program RAM
• EEPROM emulation capability using flash
• Five interrupt priority levels
— Three user programmable priority levels for each interrupt source: Level 0, 1, 2
— Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, SWI3 instruction. Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, EOnCE trace buffer
— Lowest-priority software interrupt: level LP
• Allow nested interrupt that higher priority level interrupt request can interrupt lower priority interrupt subroutine
• The masking of interrupt priority level is managed by the 56800E core
• One programmable fast interrupt that can be assigned to any interrupt source
• Notification to system integration module (SIM) to restart clock out of wait and stop states
• Ability to relocate interrupt vector table
• One multi-function, six-output pulse width modulator (PWM) module
— Up to 96 MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and edge-aligned PWM signal mode
— Phase shifting PWM pulse generation
— Four programmable fault inputs with programmable digital filter
— Double-buffered PWM registers
— Separate deadtime insertions for rising and falling edges
— Separate top and bottom pulse-width correction by means of software
— Asymmetric PWM output within both Center Aligned and Edge Aligned operation
— Separate top and bottom polarity control
— Each complementary PWM signal pair allows selection of a PWM supply source from:
– PWM generator
– Internal timers
– Analog comparator outputs
• Two independent 12-bit analog-to-digital converters (ADCs)
— 2 x 14 channel external inputs plus seven internal inputs
— Support simultaneous and software triggering conversions
— ADC conversions can be synchronized by PWM and PDB modules
— Sampling rate up to 400 KSPS for 10- or 12-bit conversion result; 470 KSPS for 8-bit conversion result
— Two 16-word result registers
• Two programmable gain amplifier (PGAs)
— Each PGA is designed to amplify and convert differential signals to a single-ended value fed to one of the ADC inputs
— 1X, 2X, 4X, 8X, 16X, or 32X gain
— Software and hardware triggers are available
— Integrated sample/hold circuit
— Includes additional calibration features:
– Offset calibration eliminates any errors in the internal reference used to generate the VDDA/2 output center point
– Gain calibration can be used to verify the gain of the overall datapath
– Both features require software correction of the ADC result
• Three analog comparators (CMPs)
— Selectable input source includes external pins, internal DACs
— Programmable output polarity
— Output can drive timer input, PWM fault input, PWM source, external pin output, and trigger ADCs
— Output falling and rising edge detection able to generate interrupts
• One dual channel 16-bit multi-purpose timer module (TMR)
— Two independent 16-bit counter/timers with cascading capability
— Up to 96 MHz operating clock
— Each timer has capture and compare and quadrature decoder capability
— Up to 12 operating modes
— Four external inputs and two external outputs
• One serial communication interface (SCI) with LIN slave functionality
— Up to 96 MHz operating clock
— Full-duplex or single-wire operation
— Programmable 8- or 9- bit data format
— Two receiver wakeup methods:
– Idle line
– Address mark
— 1/16 bit-time noise detection
• One serial peripheral interface (SPI)
— Full-duplex operation
— Master and slave modes
— Programmable length transactions (2 to 16 bits)
— Programmable transmit and receive shift order (MSB as first or last bit transmitted)
— Maximum slave module frequency = module clock frequency/2
• One inter-integrated Circuit (I2C) port
— Operates up to 400 kbps
— Supports master and slave operation
— Supports 10-bit address mode and broadcasting mode
— Supports SMBus, Version 2
• One 16-bit programmable interval timer (PIT)
— 16 bit counter with programmable counter modulo
— Interrupt capability
• One 16-bit programmable delay block (PDB)
— 16 bit counter with programmable counter modulo and delay time
— Counter is initiated by positive transition of internal or external trigger pulse
— Supports two independently controlled delay pulses used to synchronize PGA and ADC conversions with input trigger event
— Two PDB outputs can be ORed together to schedule two conversions from one input trigger event
— PDB outputs can be can be used to schedule precise edge placement for a pulsed output that generates the control signal for the CMP windowing comparison
— Supports continuous or single shot mode
— Bypass mode supported
• Computer operating properly (COP)/watchdog timer capable of selecting different clock sources
— Programmable prescaler and timeout period
— Programmable wait, stop, and partial powerdown mode operation
— Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected
— Choice of clock sources from four sources in support of EN60730 and IEC61508:
– On-chip relaxation oscillator
– External crystal oscillator/external clock source
– System clock (IPBus up to 32 MHz)
– On-chip low power 1 kHz oscillator
• Real-timer counter (RTC)
— 8-bit up-counter
— Three software selectable clock sources
– External crystal oscillator/external clock source
– On-chip low-power 1 kHz oscillator
– System bus (IPBus up to 32 MHz)
— Can signal the device to exit power down mode
• Phase lock loop (PLL) provides a high-speed clock to the core and peripherals
— Provides 3x system clock to PWM and dual timer and SCI
— Loss of lock interrupt
— Loss of reference clock interrupt
• Clock sources
— On-chip relaxation oscillator with two user selectable frequencies: 400 kHz for low speed mode, 8 MHz for normal operation
— On-chip low-power 1 kHz oscillator can be selected as clock source to the RTC and/or COP
— External clock: crystal oscillator, ceramic resonator, and external clock source
• Power management controller (PMC)
— On-chip regulator for digital and analog circuitry to lower cost and reduce noise
— Integrated power-on reset (POR)
— Low-voltage interrupt with a user selectable trip voltage of 1.81 V or 2.31 V
— User selectable brown-out reset
— Run, wait, and stop modes
— Low-power run, wait, and stop modes
— Partial power down mode
• Up to 40 general-purpose I/O (GPIO) pins
— Individual control for each pin to be in peripheral or GPIO mode
— Individual input/output direction control for each pin in GPIO mode
— Hysteresis and configurable pullup device on all input pins
— Configurable slew rate and drive strength and optional input low pass filters on all output pins
— 20 mA sink/source current
• JTAG/EOnCE debug programming interface for real-time debugging
— IEEE 1149.1 Joint Test Action Group (JTAG) interface
— EOnCE interface for real-time debugging
• Three low power modes
— Low-speed run, wait, and stop modes: 200 kHz IP bus clock provided by ROSC
— Low-power run, wait, and stop modes: clock provided by external 32–38.4 kHz crystal
— Partial power down mode
• Low power external oscillator can be used in any low-power mode to provide accurate clock to active peripherals
• Low power real time counter for use in run, wait, and stop modes with internal and external clock sources
• 32 μs typical wakeup time from partial power down modes
• Each peripheral can be individually disabled to save power
Applications
• Industrial control
• Home appliances
• Smart sensors
• Fire and security systems
• Switched-mode power supply and power management
• Power metering
• Motor control (ACIM, BLDC, PMSM, SR, and stepper)
• Handheld power tools
• Arc detection
• Medical device/equipment
• Instrumentation
• Lighting ballast
Advantages and Disadvantages
There is no relevant information available for this part yet.
ECCN / UNSPSC
ECCN | 3A991.A.2 |
HTSN: | 8542310001 |
SCHEDULE B: | 8542310000 |
Environmental & Export Classifications
Moisture Sensitivity Level (MSL) | 3(168 Hours) |
Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
Product Compliance
USHTS: | 8542310001 |
CAHTS: | 8542310000 |
CNHTS: | 8542319000 |
JPHTS: | 8542310335 |
KRHTS: | 8542311000 |
MXHTS: | 85423199 |
TARIC: | 8542319000 |
REACH SVHC: | No SVHC |
Radiation Hardening: | No |
Documents & Media
Product Manufacturer
NXP Semiconductor enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets. Built on more than 60 years of combined experience and expertise, the company has 45,000 employees in more than 35 countries.
Product Range
ARM ® PROCESSORS | ANALOG | POWER ARCHITECTURE ®PROCESSORS |
MEDIA AND AUDIO | RF | IDENTIFICATION & SECURITY |
Sensors | Wireless | Automotive Products |
Distributors
Distributors | Stock | Manufacturers | Descriptions |
Kynix | 1139 | Freescale Semiconductor - NXP | IC MCU 16BIT 12KB FLASH 28SOIC |
DigiKey | 260 | NXP USA Inc. | IC MCU 16BIT 12KB FLASH 28SOIC |
Mouser | 0 | NXP Semiconductors | Digital Signal Processors & Controllers - DSP, DSC DSC 28SOIC 12K Flash |
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