MPC8315VRAFDA Datasheets| Freescale Semiconductor - NXP| PDF| Price| In Stock

Product Overview

MPC8315VRAFDA Images are for reference only:

CAD Models

There is no relevant information available for this part yet.

Product Attributes

Product Features

• Operates at up to 400 MHz

• 16-Kbyte instruction cache, 16-Kbyte data cache

• One floating point unit and two integer units

• Software-compatible with the Freescale processor families implementing the PowerPC Architecture

• Performance monitor

• Two enhanced TSECs (eTSECs)

• Two Ethernet interfaces using one RGMII/MII/RMII/RTBI or SGMII (no GMII)

• Dual UART, one I2C, and one SPI interface

• Public key execution unit (PKEU)

— RSA and Diffie-Hellman (to 4096 bits)

— Programmable field size up to 2048 bits

— Elliptic curve cryptography (1023 bits)

— F2m and F(p) modes

— Programmable field size up to 511 bits

• Data encryption standard execution unit (DEU)

— DES, 3DES

— Two key (K1, K2) or three key (K1, K2, K3)

— ECB, CBC, CFB-64 and OFB-64 modes for both DES and 3DES

• Advanced encryption standard unit (AESU)

— Implements the Rinjdael symmetric key cipher

— Key lengths of 128, 192, and 256 bits

— ECB, CBC, CCM, CTR, GCM, CMAC, OFB, CFB, XCBC-MAC and LRW modes

— XOR acceleration

• Message digest execution unit (MDEU)

— SHA with 160-bit, 256-bit, 384-bit and 512-bit message digest

— SHA-384/512

— MD5 with 128-bit message digest

— HMAC with either algorithm

• Random number generator (RNG)

— Combines a True Random Number Generator (TRNG) and a NIST-approved Pseudo-Random Number Generator (PRNG) (as described in Annex C of FIPS140-2 and ANSI X9.62).

• Cyclical Redundancy Check Hardware Accelerator (CRCA)

— Implements CRC32C as required for iSCSI header and payload checksums, CRC32 as required for IEEE 802 packets, as well as for programmable 32 bit CRC polynomials

• Single 16- or 32-bit interface supporting both DDR1 and DDR2 SDRAM

• Support for up to 266 MHz data rate

• Support for two physical banks (chip selects), each bank independently addressable

• 64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with x8/x16 data ports (no direct x4 support)

• Support for one 16-bit device or two 8-bit devices on a 16-bit bus or two 16-bit devices on a 32-bit bus

• Support for up to 16 simultaneous open pages

• Supports auto refresh

• On-the-fly power management using CKE

• 1.8-/2.5-V SSTL2 compatible I/O

• Designed to comply with PCI Local Bus Specification Revision 2.3

• Single 32-bit data PCI interface operates at up to 66 MHz

• PCI 3.3-V compatible (not 5-V compatible)

• Support for host and agent modes

• On-chip arbitration, supporting three external masters on PCI

• Selectable hardware-enforced coherency

• Independent receive and transmit with dedicated data, clock and frame sync line

• Separate or shared RCK and TCK whose source can be either internal or external

• Glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses

• Up to 128 time slots, where each slot can be programmed to be active or inactive

• 8- or 16-bit word widths

• The TDM Transmitter Sync Signal (TFS), Transmitter Clock Signal (TCK) and Receiver Clock

• Signal (RCK) can be configured as either input or output

• Frame sync and data signals can be programmed to be sampled either on the rising edge or on the falling edge of the clock

• Frame sync can be programmed as active low or active high

• Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame

• MSB or LSB first support

• Designed to comply with USB Specification, Rev. 2.0

• Supports operation as a stand-alone USB device

— Supports one upstream facing port

— Supports three programmable USB endpoints

• Supports operation as a stand-alone USB host controller

— Supports USB root hub with one downstream-facing port

— Enhanced host controller interface (EHCI) compatible

• Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation. Low-speed operation is supported only in host mode.

• Supports UTMI+ low pin interface (ULPI) or on-chip USB-2.0 full-speed/high-speed PHY

• Supports USB on-the-go mode, which includes both device and host functionality, when using an external ULPI PHY

• PCI Express 1.0a compatible

• x1 link width

• Selectable operation as root complex or endpoint

• Both 32- and 64-bit addressing

• 128-byte maximum payload size

• Support for MSI and INTx interrupt messages

• Virtual channel 0 only

• Selectable Traffic Class

• Full 64-bit decode with 32-bit wide windows

• Dedicated descriptor based DMA engine per interface with separate read and write channels

• Designed to comply with Serial ATA Rev 2.5 Specification

• ATAPI 6+

• Spread spectrum clocking on receive

• Asynchronous notification

• Hot plug including asynchronous signal recovery

• Link power management

• Native command queuing

• Staggered spin-up and port multiplier support

• SATA 1.5 and 3.0 Gbps operation

• Interrupt driven

• Power management support

• Error handling and diagnostic features

— Far end/near end loopback

— Failed CRC error reporting

— Increased ALIGN insertion rates

— Scrambling and CONT override

• Two SGMII/RGMII/MII/RMII/RTBI interfaces

• Two controllers designed to comply with IEEE Std 802.3™, IEEE 802.3u™, IEEE 802.3x™, IEEE 802.3z™, IEEE 802.3au™, IEEE 802.3ab™, and IEEE Std 1588™

• Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating mode

• MII management interface for external PHY control and status.

• Provides power management when the device is used in both PCI host and agent modes

• PCI Power Management 1.2 D0, D1, D2, D3hot, and D3cold states

• PME generation in PCI agent mode, PME detection in PCI host mode

• Wake-up from Ethernet (magic packet), USB, GPIO, and PCI (PME input as host) while in the D1, D2 and D3hot states

• A new low-power standby power management state called D3warm

— The PMC, one Ethernet port, and the GTM block remain powered via a split power supply controlled through an external power switch

— Wake-up events include Ethernet (magic packet), GTM, GPIO, or IRQ inputs and cause the device to transition back to normal operation

— PCI agent mode is not be supported in D3warm state

• PCI Express-based PME events are not supported

• Allows chaining (both extended and direct) through local memory-mapped chain descriptors (accessible by local masters)

• Misaligned transfer capability for source/destination address

• Supports external DREQ, DACK and DONE signals

Applications

There is no relevant information available for this part yet.

Advantages and Disadvantages

There is no relevant information available for this part yet.

ECCN / UNSPSC

Environmental & Export Classifications

Product Compliance

Documents & Media

Product Manufacturer

NXP Semiconductor enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets. Built on more than 60 years of combined experience and expertise, the company has 45,000 employees in more than 35 countries.

Product Range

Distributors

Alternative Models

There is no relevant information available for this part yet.

Popularity by Region

Market Price Analysis

There is no relevant information available for this part yet.

You May Also Be Interested In：

Ordering & Quality

Photo	Mfr. Part #	Company	Description	Package	PDF	Qty	Pricing (USD)
	DRV8801PWP	Company:Texas Instruments	Remark:36-V， 2.8-A h-bridge motor driver with current feedback 16-HTSSOP -40 to 85	Package:HTSSOP, TSSOP16,.25	N/A	In Stock:On Order Inquiry	Price: Call	Inquiry
	MPC17531ATEP	Company:NXP Semiconductors	Remark:STEPPER MOTOR CONTROLLER， 1.4A， QCC24	Package:HVQCCN, LCC24,.16SQ,20	N/A	In Stock:On Order Inquiry	Price: Call	Inquiry
	MC33926PNB	Company:NXP Semiconductors	Remark:BRUSH DC MOTOR CONTROLLER， QCC32	Package:HQCCN, LCC32,.32SQ,32	N/A	In Stock:On Order Inquiry	Price: Call	Inquiry