Product Overview
Kynix Part #: | KY32-MPC8360EVVALFHA |
Manufacturer Part#: | MPC8360EVVALFHA |
Product Category: | Embedded - Microprocessors |
Stock: | Yes |
Manufacturer: | Freescale Semiconductor - NXP |
Click Purchase button to buy original genuine MPC8360EVVALFHA |
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Description: | IC MPU MPC83XX 667MHZ 740TBGA |
Datasheet: | MPC8360EVVALFHA Datasheet |
Package: | 740-LBGA |
Quantity: | 512 PCS |
MPC8360EVVALFHA Images are for reference only:
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Product Attributes
Manufacturer: | Freescale Semiconductor - NXP |
Product Category: | Embedded - Microprocessors |
Status: | Active |
Series: | MPC83xx |
Address Bus Width: | 32.0 |
Bit Size: | 32 |
Boundary Scan: | Yes |
Core Processor: | PowerPC e300 |
Co-Processors/DSP: | Communications; QUICC Engine, Security; SEC |
Clock Frequency-Max: | 66.67 MHz |
Device Core: | PowerQUICC II Pro |
Data Bus Width: | 32 bit |
Display & Interface Controllers | - |
Ethernet: | 10/100/1000Mbps (1) |
EU RoHS Compliant: | Yes |
External Data Bus Width: | 32.0 |
Format: | FLOATING POINT |
Frequency: | 667 MHz |
Graphics Acceleration: | No |
Interface: | I2C, SPI, UART, USB |
Interface Type: | Ethernet, I2C, PCIe, SPI, UART, USB |
Instruction Type: | Floating Point |
Integrated Cache: | Yes |
Instruction Set Architecture: | RISC |
JESD-30 Code: | S-PBGA-B740 |
JESD-609 Code: | e1 |
Length: | 37.5 mm |
Lead Finish: | Tin/Silver |
Low Power Mode: | Yes |
Memory Size: | 64 kB |
Memory Type: | L1 Cache |
Mounting-Style: | SMD/SMT |
Maximum Clock Frequency: | 667 MHz |
Number of Bits: | 32 |
Number of Pins: | 740 |
Number of Timers | 4 |
Number of Terminals: | 740 |
Number of CPU Cores: | 1 |
Operating Temperature-Min: | 0°C |
Operating Temperature-Max: | 105°C |
Pin Count: | 740 |
Power Supplies: | 1.8/2.5,3.3 |
Package/Case: | 740-LBGA |
Package Style: | GRID ARRAY, LOW PROFILE |
Package Shape: | SQUARE |
Package Code: | LBGA |
Package Body Material: | PLASTIC/EPOXY |
Package Equivalence Code: | BGA740,37X37,40 |
Peak Reflow Temperature: | 260 °C |
RAM Controllers: | DDR, DDR2 |
REACH Compliant: | Yes |
SATA: | - |
Speed: | 667.0 MHz |
Sub Category: | Microprocessors |
Surface Mount: | Yes |
Security Features: | Cryptography, Random Number Generator |
Seated Height-Max: | 1.69 mm |
Supply Voltage-Nom: | 1.3 V |
Supply Voltage-Min: | 1.25 V |
Supply Voltage-Max: | 1.35 V |
Supplier Device Package: | 740-TBGA (37.5x37.5) |
Tradename: | PowerQUICC |
Technology: | CMOS |
Terminal Form: | BALL |
Terminal Pitch: | 1.0 mm |
Terminal Finish: | Tin/Silver/Copper (Sn/Ag/Cu) |
Terminal Position: | BOTTOM |
Time@Peak Reflow Temperature-Max: | 40 s |
USB: | USB 1.x (1) |
Unit Weight: | 0.380828 oz |
Width: | 37.5 mm |
Product Features
• e300 PowerPC processor core (enhanced version of the MPC603e core)
— Operates at up to 667 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E)
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the Freescale processor families implementing the Power Architecture™ technology
• QUICC Engine unit
— Two 32-bit RISC controllers for flexible support of the communications peripherals, each operating up to 500 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E)
— Serial DMA channel for receive and transmit on all serial channels
— QUICC Engine module peripheral request interface (for SEC, PCI, IEEE Std. 1588™)
— Eight universal communication controllers (UCCs) on the MPC8360E and six UCCs on the MPC8358E supporting the following protocols and interfaces (not all of them simultaneously):
– IEEE 1588 protocol supported
– 10/100 Mbps Ethernet/IEEE Std. 802.3™ CDMA/CS interface through a media-independent interface (MII, RMII, RGMII)1
– 1000 Mbps Ethernet/IEEE 802.3 CDMA/CS interface through a media-independent interface (GMII, RGMII, TBI, RTBI) on UCC1 and UCC2
– 9.6-Kbyte jumbo frames
– ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1, and AAL5 in accordance ITU-T I.363.5
– ATM AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex (with 4 CPS packets per cell) in accordance ITU-T I.366.1 and I.363.2
– ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM forum TM4.1 for up to 64-Kbyte simultaneous ATM channels
– ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance with ITU-T I.163.1 and ATM Forum af-vtoa-00-0078.000
– IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in accordance with the ATM forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001 (Version 1.1)
– ATM Transmission Convergence layer support in accordance with ITU-T I.432
– ATM OAM handling features compatible with ITU-T I.610
– PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the following RFCs: 1661, 1662, 1990, 2686, and 3153
– IP support for IPv4 packets including TOS, TTL, and header checksum processing
– Ethernet over first mile IEEE 802.3ah
– Shim header
– Ethernet-to-Ethernet/AAL5/AAL2 inter-working
– L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q™ VLAN tags
– ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including bridging of ATM ports to Ethernet ports
– Extensive support for ATM statistics and Ethernet RMON/MIB statistics
– AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate
– Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY
– POS hardware; microcode must be loaded as an IRAM package
– Transparent up to 70-Mbps full-duplex
– HDLC up to 70-Mbps full-duplex
– HDLC BUS up to 10 Mbps
– Asynchronous HDLC
– UART
– BISYNC up to 2 Mbps
– User-programmable Virtual FIFO size
– QUICC multichannel controller (QMC) for 64 TDM channels
— One multichannel communication controller (MCC) only on the MPC8360E supporting the following:
– 256 HDLC or transparent channels
– 128 SS7 channels
– Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces
— Two UTOPIA/POS interfaces on the MPC8360E supporting 124 MultiPHY each (optional 2*128 MultiPHY with extended address) and one UTOPIA/POS interface on the MPC8358E supporting 31/124 MultiPHY
— Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management
— Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with 1-bit mode for E3/T rates in clear channel
— Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC and MCC serial channels (MCC is only available on the MPC8360E)
— Four independent 16-bit timers that can be interconnected as four 32-bit timers
— Interworking functionality:
– Layer 2 10/100-Base T Ethernet switch
– ATM-to-ATM switching (AAL0, 2, 5)
– Ethernet-to-ATM switching with L3/L4 support
– PPP interworking
• Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, 802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs).
— Public key execution unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
— Data encryption standard execution unit (DEU)
– DES, 3DES
– Two key (K1, K2) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)
— Implements the Rinjdael symmetric key cipher
— Key lengths of 128, 192, and 256 bits, two key
– ECB, CBC, CCM, and counter modes
— ARC four execution unit (AFEU)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message digest execution unit (MDEU)
– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either SHA or MD5 algorithm
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
— Storage/NAS XOR parity generation accelerator for RAID applications
• Dual DDR SDRAM memory controllers on the MPC8360E and a single DDR SDRAM memory controller on the MPC8358E
— Programmable timing supporting both DDR1 and DDR2 SDRAM
— On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus; on the MPC8358E, the DDR bus can be configured as a 32- or 64-bit bus
— 32- or 64-bit data interface, up to 333 MHz (for the MPC8360E) and 266 MHz (for the MPC8358E) data rate
— Four banks of memory, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gigabit with ×8/×16 data ports
— Full ECC support (when the MPC8360E is configured as 2×32-bit DDR memory controllers, both support ECC)
— Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open pages for DDR2)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep mode support for self refresh SDRAM
— Supports auto refreshing
— Supports source clock mode
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
— External driver impedance calibration
— On-die termination (ODT)
• PCI interface
— PCI Specification Revision 2.3 compatible
— Data bus widths:
– Single 32-bit data PCI interface that operates at up to 66 MHz
— PCI 3.3-V compatible (not 5-V compatible)
— PCI host bridge capabilities on both interfaces
— PCI agent mode supported on PCI interface
— Support for PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Support for posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration, supporting five masters on PCI
— Support for accesses to all PCI address spaces
— Parity support
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle supported when the device is the target
— Internal configuration registers accessible from PCI
• Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
• Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for one external (optional) and seven internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to communication processor
— Redirects interrupts to external INTA pin when in core disable mode
— Unique vector number for each interrupt source
• Dual industry-standard I2C interfaces
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
— System initialization data is optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware
• DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— All channels accessible by local core and remote PCI masters
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain
— DMA external handshake signals: DMA_DREQ[0:3]/DMA_DACK[0:3]/DMA_DONE[0:3]. There is one set for each DMA channel. The pins are multiplexed to the parallel IO pins with other QE functions.
• DUART
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
• System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers
• IEEE Std. 1149.1™-compliant, JTAG boundary scan
• Integrated PCI bus and SDRAM clock generation
Applications
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Advantages and Disadvantages
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ECCN / UNSPSC
ECCN | 5A002.A.1 |
HTSN: | 8542310001 |
SCHEDULE B: | 8542310000 |
Environmental & Export Classifications
Moisture Sensitivity Level (MSL) | 3(168 Hours) |
Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
Product Compliance
USHTS: | 8542310001 |
CAHTS: | 8542310012 |
CNHTS: | 8542319000 |
JPHTS: | 8542310313 |
KRHTS: | 8542311000 |
MXHTS: | 85423199 |
TARIC: | 8542319000 |
Halogen Free: | Halogen Free |
REACH SVHC: | No SVHC |
Radiation Hardening: | No |
Documents & Media
Product Manufacturer
NXP Semiconductor enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets. Built on more than 60 years of combined experience and expertise, the company has 45,000 employees in more than 35 countries.
Product Range
ARM ® PROCESSORS | ANALOG | POWER ARCHITECTURE ®PROCESSORS |
MEDIA AND AUDIO | RF | IDENTIFICATION & SECURITY |
Sensors | Wireless | Automotive Products |
Distributors
Distributors | Stock | Manufacturers | Descriptions |
Kynix | 512 | Freescale Semiconductor - NXP | IC MPU MPC83XX 667MHZ 740TBGA |
DigiKey | 21 | NXP USA Inc. | IC MPU MPC83XX 667MHZ 740TBGA |
Mouser | 21 | NXP Semiconductors | Microprocessors - MPU 8360 TBGA ENCRP NO-PB |
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