Product Overview
Kynix Part #: | KY32-MSC8144VT800A |
Manufacturer Part#: | MSC8144VT800A |
Product Category: | Embedded - DSP (Digital Signal Processors) |
Stock: | Yes |
Manufacturer: | Freescale Semiconductor - NXP |
Click Purchase button to buy original genuine MSC8144VT800A |
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Description: | IC DSP QUAD 800MHZ 783FCBGA |
Datasheet: | MSC8144VT800A Datasheet |
Package: | 783-BBGA, FCBGA |
Quantity: | 15462 PCS |
MSC8144VT800A Images are for reference only:
CAD Models
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Product Attributes
Manufacturer: | Freescale Semiconductor - NXP |
Product Category: | Embedded - DSP (Digital Signal Processors) |
Bit Size: | 16 |
Barrel Shifter: | No |
Boundary Scan: | Yes |
Clock Frequency-Max: | 133.0 MHz |
Data Bus Width: | 32 bit |
EU RoHS Compliant: | Yes |
Format: | FIXED POINT |
Frequency: | 800 MHz |
Interface: | Ethernet, I2C, SPI, UART |
Internal Bus Architecture: | MULTIPLE |
JESD-30 Code: | S-PBGA-B783 |
JESD-609 Code: | e2 |
Length: | 29.0 mm |
Low Power Mode: | No |
Number of Pins: | 783 |
Number of Terminals: | 783 |
Power Supplies: | 1.2,1.8,2.5,3.3 |
Package Style: | GRID ARRAY |
Package Shape: | SQUARE |
Package Code: | BGA |
Package Body Material: | PLASTIC/EPOXY |
Package Equivalence Code: | BGA783,28X28,40 |
Peak Reflow Temperature: | 245 °C |
RAM Size: | 10.5 MB |
RAM (words): | 16384 |
Sub Category: | Digital Signal Processors |
Surface Mount: | Yes |
Seated Height-Max: | 3.176 mm |
Supply Voltage-Nom: | 1.0 V |
Supply Voltage-Min: | 0.97 V |
Supply Voltage-Max: | 1.05 V |
Technology: | CMOS |
Terminal Form: | BALL |
Terminal Pitch: | 1.0 mm |
Terminal Finish: | TIN SILVER |
Terminal Position: | BOTTOM |
Time@Peak Reflow Temperature-Max: | 30 s |
Width: | 29.0 mm |
Product Features
• Four StarCore® SC3400 DSP subsystems, each with an SC3400 DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, and low-power Wait and Stop processing modes.
• Chip-level arbitration and system (CLASS) that provides full fabric non-blocking arbitration between the processing elements and other initiators and the M2 memory, DDR SRAM controller, device configuration control and status registers, and other targets.
• 128 Kbyte L2 shared instruction cache.
• 512 Kbyte M2 memory for critical data and temporary data buffering.
• 10 Mbyte 128-bit wide M3 memory.
• 96 Kbyte boot ROM.
• Three input clocks (shared, global, and differential).
• Four PLLs (system, core, global, and serial RapidIO).
• DDR controller with up to a 200 MHz clock (400 MHz data rate), 16/32 bit data bus, supporting up to 1 Gbyte in up to two banks and support for DDR1 and DDR2.
• DMA controller with 16 bidirectional channels with up to 1024 buffer descriptors, and programmable priority, buffer, and multiplexing configuration.
• Up to eight independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 128 Mbps data rate for all channels, with glueless interface to E1 or T1 framers, and can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97.
• QUICC Engine™ technology subsystem with dual RISC processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction RAM, supporting three communication controllers with one ATM and two Gigabit Ethernet interfaces, to offload scheduling tasks from the DSP cores.
– The two Ethernet controllers support 10/100/1000 Mbps operations via MII/RMII/SMII/RGMII/SGMII and the SGMII protocol using a 4-pin SerDes interface at 1000 Mbps data rate only.
– The ATM controller supports UTOPIA level II 8/16 bits at 25/50 MHz in UTOPIA/POS mode with adaptation layer support AAL0, AAL2, and AAL5.
• PCI designed to comply with the PCI specification revision 2.2 at 33 MHz or 66 MHz with access to all PCI address spaces.
• Serial RapidIO® 1x/4x endpoint corresponds to Specification 1.2 of the RapidIO trade association, and supports read, write, messages, doorbells, and maintenance accesses in inbound mode, and messages and doorbells in outbound mode.
• I/O interrupt concentrator consolidates all chip maskable interrupt and non-maskable interrupt sources and routes them to INT_OUT, NMI_OUT, and the cores.
• UART that permits full-duplex operation with a bit rate of up to 6.25 Mbps.
• Serial peripheral interface (SPI).
• Four timer modules, each with four configurable16-bit timers.
• Four software watchdog timer (SWT) modules.
• Up to 32 general-purpose input/output (GPIO) ports, 16 of which can be configured as maskable interrupt inputs.
• I2C interface that allows booting from EEPROM devices.
• Eight programmable hardware semaphores.
• Thirty two virtual maskable interrupts and one virtual NMI that can be generated by a simple write access.
• Optional booting via serial RapidIO port, PCI, I2C, SPI, or Ethernet interfaces.
Applications
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Advantages and Disadvantages
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ECCN / UNSPSC
There is no relevant information available for this part yet.
Environmental & Export Classifications
Moisture Sensitivity Level (MSL) | 3(168 Hours) |
Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
Product Compliance
There is no relevant information available for this part yet.
Documents & Media
Product Manufacturer
NXP Semiconductor enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets. Built on more than 60 years of combined experience and expertise, the company has 45,000 employees in more than 35 countries.
Product Range
ARM ® PROCESSORS | ANALOG | POWER ARCHITECTURE ®PROCESSORS |
MEDIA AND AUDIO | RF | IDENTIFICATION & SECURITY |
Sensors | Wireless | Automotive Products |
Distributors
Distributors | Stock | Manufacturers | Descriptions |
Kynix | 15462 | Freescale Semiconductor - NXP | IC DSP QUAD 800MHZ 783FCBGA |
DigiKey | - | - | - |
Mouser | - | - | - |
Alternative Models
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Popularity by Region
Market Price Analysis
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