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Dec 22 2017

Integrate Circuit History and Its Packaging Types

Warm hints: The word in this article is about 4600 and reading time is about 28 minutes.


An integrated circuit (integrated circuit) is a micro electronic device or component. With certain techniques, the transistor, required a circuit of resistance, capacitance and inductance components and interconnect wiring together, produced in a small or a few bits of the semiconductor wafer or substrate, and then encapsulated in a tube shell, a micro structure required for the circuit function; all of them element in the structure has formed a whole, so that the electronic components to miniaturization, low power consumption, high reliability and intelligent a huge step forward. It is represented by the letter "IC" in the circuit. The inventors of integrated circuits are Jack Kilby (Ge based integrated circuits) and Robert Nois (silicon based (Si) integrated circuits). Nowadays, most of the applications of semiconductor industry are silicon based integrated circuits. This article mainly shows the packaging types of integrate circuit and its history.

Article Core

Integrate Circuit History and Its Packaging Types


A micro electronic device or component

English name

Integrate Circuit




Jack Kilby


Miniaturized the circuit



I.The history of world integrated circuits

II.The history of the development of integrated circuits in China

III.The significance of the various parts of the integrated circuit model

IV.Development countermeasures and suggestions


I.The history of world integrated circuits

  • In 1947,John Bardin,Bratton,Shockley who in the Baer Laboratory located in US invented the transistor,which is the first milestone in the development of microelectronics technology.

  • In 1950,Junction transistor came out.

  • In 1951,the invention of field effect transistor

  • In 1956,C S Fuller invented the diffusion process

  • In 1958,Robert Noyce of Fairchild Corp and the the Kirby of Deyi invented the integrated circuit several months respectively, creating the history of the world microelectronics.

  • In 1960: H H Loor and E Castellani invented the photolithography process

  • In 1962: the MOS field effect transistor developed by RCA company in the United States

  • In 1963: F.M.Wanlass and C.T.Sah proposed CMOS technology for the first time. Today, more than 95% of integrated circuit chips are based on CMOS Technology

  • In 1964: Intel Moore puts forward Moore's law, which predicts the integration of transistors will increase by 1 times every 18 months.

  • In 1966: RCA company developed CMOS IC and developed the first gate array (50 gates), which laid a solid foundation for the development of large scale integrated circuits, and has milestone significance.

  • In 1979: Intel launches 5MHz 8088 microprocessors, and then IBM launches the world's first PC based on 8088

  • In 1981: 256Kb DRAM and 64KB CMOS SRAM came out

  • In 1984: Japan announced the introduction of 1Mb DRAM and 256Kb SRAM

  • In 1985: 80386 microprocessors come out, 20MHz

  • In 1988: 16M DRAM came out, and 1 square centimeter sized silicon chips were integrated with 35 million transistors, marking the stage of entering the ultra large scale integrated circuit (VLSI) stage.

  • In 1989: 1Mb DRAM enters the market

  • In 1989: 486 microprocessors, 25MHz, 1 micron m, and later 50MHz chips using 0.8 micron M

  • In 1992: 64M bit random access memory came out

  • In 1993: 66MHz Pentium processor is introduced, using 0.6 micron m process

  • In 1995: Pentium Pro, 133MHz, using 0.6-0.35 M technology;

  • In 1997: 300MHz Pentium II came out, using 0.25 micron m process

  • In1999: Pentium III came out, 450MHz, using 0.25 micron m process, then 0.18 micron m process

  • In 2000: 1Gb RAM launched the market

  • In 2000: Pentium 4, 1.5GHz, using a 0.18 - M process

  • In 2001: Intel announced the adoption of a 0.13 - M process in the second half of 2001.

  • In 2003: Pentium 4 E series, the use of 90nm technology.

  • In 2005: Intel Core 2 series listed by 65nm technology.

  • In 2007: Based on the new 45 nanometer High-K process Intel Core 2 E7/E8/E9 listed.

  • In 2009: Intel Core I series launched a new record, using the 32 nanometer process leading, and the 22 nanometer technology is developing the next generation.

II.The history of the development of integrated circuits in China

The integrated circuit industry in China was born in 60s and has undergone three stages of development:

In 1965 -1978: with the goal of supporting computers and military industry, and developing logic circuits as the main products, the supporting conditions of integrated circuit industry foundation and related equipments, instruments and materials were initially established.

1978 -1990: the main imported second-hand equipment, improve the level of integrated circuit equipment, in the "governance scattered disorder" at the same time, to the consumer as the supporting point, to solve the domestic color TV integrated circuit

In 1990 -2000: focusing on the 908 project and the 909 project, and taking CAD as the breakthrough point, we focused on the construction of scientific and technological research bases and the research and development base in the north, serving the information industry, and the integrated circuit industry has made new progress.

integrate circuit

The integrated circuit industry is the overall market for each part of the integrated circuit industry chain sales, which include not only the IC market, including IP market, EDA market, nuclear chip foundry market, packaging market, and even extended to the equipment and materials market.

The IC industry is no longer dependent on the development of single devices such as CPU and memory. Mobile Internet, triple play, multi screen interaction and intelligent terminals bring multiple market space, and business mode is constantly innovating to inject new vitality into the market. At present, China's IC industry has a certain basis, over the years of technological innovation vitality of China's IC industry, the accumulation of power market development ability, integration of resources and vast market potential, laid the foundation for the industry in the next 5 years to 10 years to achieve rapid development, to a new stage.


III.The significance of the various parts of the integrated circuit model


First part

Second part

Third part

Forth part











C represents Chinese manufacturing


TTL circuit

Using numbers to represent the serial code of the device




Multilayer ceramic flat


HTL circuit




Plastic flat


ECL circuit




Black Flat


Black Flat


CMOS circuit




Multi-layer ceramic double row straight






Black dip


micromachine circuit




Double row of plastic


Linear amplifier


Single row of plastic




Metal rhombus


Nonlinear circuit


Metal circle


interface circuit


ceramic chip carrier


A/D Converter




D/A Converter


Needle grid display


Audio and TV circuit


Special communication circuit


Sensitive circuit


Clock circuit

Take an example:

l Schottky CT54S20MD, 4 INPUT NAND gate

C - conforms to national standards

T-TTL circuit


1. BGA(Ball Grid Array)

A spherical contact array, one of the surface mount packages. A spherical bump is made by means of array on the back of the printed substrate instead of pins. The LSI chip is assembled on the front side of the printed substrate, and then sealed by molding resin or potting method. It is also known as the convex point array carrier (PAC). The pin can be over 200, and it is a package for multi pin LSI. The encapsulated body can also be done smaller than the QFP (four side pin flat package). For example, the 360 pin BGA with the pin center distance of 1.5mm is only the 31mm square, and the 304 pin QFP of the pin center distance is 0.5mm. And BGA doesn't have to worry about the problem of pin deformation like QFP.

Integrate circuit

2. BQFP (Quad Flat Package with Bumper)

Four side pin flat packaging with cushions. One of the QFP packages is to set up the protrusions (cushions) at the four corners of the package to prevent the pin from bending during the delivery. American semiconductor manufacturers mainly use this package in microprocessors and ASIC circuits. The pin center is 0.635mm, and the number of pins is about 84 to 196 (see QFP).

3. C- (Ceramic)

Indicating the mark of the ceramic package. For example, CDIP represents ceramic DIP. A mark that is often used in practice


A glass sealed ceramic double row plug - in package is used for ECL RAM, DSP (digital signal processor) and other circuits. Cerdip with glass window is used for UV erasure type EPROM and microprocessor-based circuits with EPROM inside. The pin center is 2.54mm, and the number of pins is from 8 to 42. In Japan, this package is represented as DIP G (G means glass seal).


One of the surface mount packages, that is, the sealed ceramic QFP, is used to encapsulate the logical LSI circuits of DSP and so on. The Cerquad with a window is used to encapsulate the EPROM circuit. The heat dissipation is better than that of plastic QFP, and the power of 1.5 ~ 2W can be allowed under the condition of natural air cooling. But the cost of packaging is 3~5 times higher than that of plastic QFP. The pin center distance has many specifications such as 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm and so on. The number of pins is from 32 to 368.

Integrate circuit

CLCC, one of surface mount package, pin out from four sides of a T-shaped package. The windows are used to encapsulate the UV erasure type EPROM and the microprocessor-based circuits with EPROM. This package is also known as QFJ, QFJ - G (see QFJ).

6.COB (Chip on Board)

Chip on board package is bare chip mounting technology of semiconductor chip transfer mounted on the printed circuit board, electrical connecting chip and substrate with suture method of electrical leads, the chip and the substrate with the suture method of lead, and covered with resin to ensure the reliability of the. Although COB is the most simple bare chip mounting technology, but it is far better than the TAB package density and rewind welding technology.

7. DFP (Dual Flat Package)

Double side pin flat package. It's an alias of SOP (see SOP). There had been this method before, and it was basically not used in the late 80s.

8. DIC(Dual In-Line Ceramic Package)

An alias of ceramic DIP (containing glass seal) (see DIP).

9. DIL (Dual in-Line)

An alias of DIP(see DIP),european semiconductor manufacturers often use this name.

10. DIP (Dual In-Line Package)

Double row plug - in package. One of the intercalated packages, the pin is drawn from both sides of the package, and the packaging material has two kinds of plastic and ceramic. DIP is the most popular plug - in package. The application range includes standard logic IC, memory LSI, microcomputer circuit and so on. The pin center is 2.54mm, and the number of pins is from 6 to 64. The package width is usually 15.2mm. Some packages with a width of 7.52mm and 10.16mm are called skinny DIP and slim DIP (narrow DIP), respectively. But in most cases, there is no distinction. It is simply called DIP. In addition, ceramic DIP, which is sealed with low melting point glass, is also called cerdip (see cerdip).

Integrate circuit packaging

11. DSO(Dual Small Out-Lint)

The two sides pin small shape package. SOP's alias (see SOP). Some semiconductor manufacturers use this name.

12. DICP(Dual Tape Carrier Package)

The two side pins are loaded with load. One of the TCP (on load package). The pin is made on the insulation belt and extracted from both sides of the package. Because of the use of TAB (automatic load welding) technology, the package shape is very thin. It is commonly used in LCD driver LSI, but most of them are fixed products. In addition, the 0.5mm thick memory LSI book package is at the development stage. In Japan, DICP is named DTP according to the standard of EIAJ (Japanese electronic machinery industry).

13. DIP (dual tape carrier package)

Ditto. The standard of the Japanese electronic machinery industry will be named for DTCP (see DTCP).

14.FP (flat package)

Flat packaging. One of the surface mount packages. The alias of QFP or SOP (see QFP and SOP). Some semiconductor manufacturers use this name.


Reverse welding chip. One of the bare chip packaging technologies is to make metal bumps in the electrode area of the LSI chip, then press the metal bump to the electrode area on the printed substrate. The possession area of the package is basically the same as the chip size. It is the smallest and thinnest of all packaging technology. However, if the thermal expansion coefficient of the substrate is different from that of the LSI chip, the reaction will be generated at the joint, which affects the reliability of the connection. Therefore, it is necessary to use the resin to reinforce the LSI chip and use the substrate material with the same thermal expansion coefficient.

16. FQFP (fine pitch quad flat package)

The small pin center is QFP. QFP usually refers to the pin center distance less than 0.65mm (see QFP). This name is used by the part of the conductor manufacturer.

integrate circuit packagin

17.CPAC (globe top pad array carrier)

American Motorola company's alias to BGA (see BGA).

18.CQFP (quad fiat package with guard ring)

Four side pin flat package with protective ring. One of the plastic QFP pins is masking with a resin protective ring to prevent bending. Before the LSI is assembled on the printed substrate, the pins are cut off from the protection ring and made to make the seagull winged (L shape). This package has been produced in mass production by the Motorola company in the United States. The center of the pin is 0.5mm, and the number of pins is up to 208.

19.H- (with heat sink)

Indicate the mark with the radiator. For example, HSOP represents a SOP with a radiator.

20. pin grid array(surface mount type)

Surface mount type PGA. Usually PGA is a plug - in package with a pin length of about 3.4mm. The surface mount PGA has a display pin on the bottom of the package, and its length is from 1.5mm to 2.0mm. The method of bonding with the printed substrate is also called the collision PGA. Because the center distance between pins is only 1.27mm, which is half less than that of plug-in PGA, so the packaging body can not be made very large, and the number of pins is much more than that of cartridge type (250~528), which is the package for large-scale logic LSI. The substrate is packed with multilayer ceramic substrate and glass epoxy resin printing base. The packaging with multilayer ceramic substrate has been applied.

21. JLCC (J-leaded chip carrier)

J - shaped pin chip carrier. Refer to the alias with the window CLCC and the ceramic QFJ with the window (see CLCC and QFJ). The name used by some semiconductor manufacturers.

22. LCC(Leadless Chip Carrier)

Non pin chip carrier. It refers to the four sides of the ceramic substrate which only contact the electrode and have no pin surface mount type package. High speed and high frequency IC package, also known as QFN or QFNC ceramics (see QFN).

23. LGA(Land Grid Array)

Contact display package. That is, a package with an array state electrode contact is made at the bottom. Insert the socket into the socket. The ceramic LGA, which has 227 contacts (1.27mm center distance) and 447 contact (2.54mm center distance), is now applied to high speed logic LSI circuits. Compared with QFP, LGA can accommodate more input and output pins in smaller packages. In addition, because the impedance of the lead is small, it is very suitable for high speed LSI. However, because of the complex production of sockets and high cost, it was basically not used in 90s. The demand for it is expected to increase in the future.

24. LOC(lead on Chip)

The lead package on the chip. One of the technologies of LSI encapsulation is that the leading part of the lead frame is located on the top part of the chip. There is a convex solder spot near the center of the chip, and the electrical connection is made by wire suture. Compared with the structure that originally arranged the lead frame near the side of the chip, the chip contained in the same size package has a width of about 1mm.

25. LQFP(Low Profile Quad Flat Package)

Thin QFP. The QFP, which encapsulates the thickness of 1.4mm, is the name used by the Japanese electronic machinery industry according to the specifications of the new QFP.

26.COF(Chip On Flex,or Chip On Film, or flip chip film)

Fix the IC on the flexible circuit board grain soft film technology, which using soft additional circuit boards as packaging chip carrier, put the chip and soft circuit board joint together.


integrate circuit packaging

27.COG(Chip on glass)

 The chip is binding on the glass directly .This approach can greatly reduce the volume of the entire LCD module, and easy for mass production, apply for consumer electronic products, such as mobile phone, PDA, etc.

28.DIP(dual in-line package)

Dual in-line package, one of the Cartridge type packaging, the pins lead to both sides of packaging, there are two kinds of packaging materials, plastic and ceramic. DIP is the most popular Cartridge type packaging, applications include standard logic IC, memory LSI, microcomputer circuit, etc. Pin center distance of 2.54 mm, pin number from 6 to 64. Packaging width usually is 15.2 mm. Some are 7.52 mm and 10.16 mm respectively called skinny DIP and slim DIP (narrow size DIP). But in most cases is not distinction, simply referred to as DIP. In addition, with low melting point glass sealed ceramic DIP also called cerdip.


P-Plasti, is the mark for plastic packaging. e.g. PDIP represents plastic DIP.

30.SDIP (shrink dual in-line package)

Shrink type DIP, one of cartridge type packaging, same shape as DIP, but the pin center distance (1.778 mm) is less than the DIP (2.54 mm), so name it. Pin number from 14 to 90. Also called SH-DIP. There are two kinds of materials, ceramic and plastic.+

30.SKDIP/SKY(Skinny Dual In-line Packages)

 One of the DIPs. With width of 7.62 mm, pin center distance of 2.54 mm, narrow size DIP, often also called DIP (refer to DIP).


 One of the DIPs.


 C-ceramic, ceramic packing mark. For example, CDIP represents ceramic DIP. In practice, which is often used.

33.DICP(dual tape carrier package)

 Dual pin tape carrier packaging. One of the TCP (with carrier packaging). Pin production lead from the insulated tape on both sides of the packaging. Due to the use of TAB (with automatic welding) technology, packaging shape is very thin. Often used for liquid crystal display driver LSI, but most are customized. In addition, 0.5 mm thin shape memory LSI packaging is under development. In Japan, according to the EIAJ(Japan electronic machinery industry) standards, named DICP as DTP.+

34. SOI(small out-line I-leaded package)

Shape I pin small outer package. One of the surface mount packages. The pin leads down from the package to the I, and the center is 1.27mm. The possession area is less than SOP. Hitachi company in the simulation of IC (with IC drive motor) used in this package. The pin number is 26.

35. SOIC(small out-line integrated circuit)

SOP's alias (see SOP). There are many semiconductor manufacturers abroad to use this name.

36. SOJ(Small Out-Line J-Leaded Package)

Shape J pin small outer package. One of the surface mount packages. The pin leads down from the sides of the package to the shape of J, so it is named. Most commonly used in plastic products, most of them are used in DRAM and SRAM LSI circuits, but most of them are DRAM. Many of the DRAM devices packaged in SO J are assembled on SIMM. The pin center is 1.27mm, and the number of pins is from 20 to 40 (see SIMM).

integrate circuit packaging

37.SQL(Small Out-Line L-leaded package)

The name adopted by the JEDEC (United States Joint Electronic Equipment Engineering Committee) standard for SOP (see SOP).

38. SONF(Small Out-Line Non-Fin)

SOP without heat sink. The same as the usual SOP. In order to indicate the difference of the heat sink in the power IC package, the NF (non-fin) label is intentionally added. The name used by some semiconductor manufacturers (see SOP).

39. SOP(small Out-Line package)

Small shape package. One of the surface mount packages, which leads to the gull wing (L shaped) from both sides of the package. There are two kinds of materials, plastic and ceramics. Also called SOL and DFP.

In addition to the memory LSI, SOP is also widely used in small scale ASSP and other circuits. In the area of no more than 10~40 of the input and output terminals, SOP is the most popular surface mount package. The pin center is 1.27mm, and the number of pins is 8~44.

In addition, the SOP of the pin center distance less than 1.27mm is also called SSOP, and the SOP with a height of less than 1.27mm is also called TSOP (see SSOP, TSOP). And a SOP with a radiator.

40. SOW(Small Outline Package(Wide-Jype))

Wide body SOP. The name used by some semiconductor manufacturers.

41. SLDIP(slim dual in-line package)

A kind of DIP. It refers to a narrow body DIP with a width of 10.16mm and a center distance of 2.54mm. It is commonly referred to as DIP.

42. SMD(surface mount devices)

Surface mounting device. Occasionally, some semiconductor manufacturers attribute SOP to SMD (see SOP).

SOP's alias. Many semiconductor manufacturers in the world use this nickname. (see SOP).

integrate circuit packaging

43. SIMM(single in-line memory module)

A single column memory component. A memory module with electrodes only near a side of the printed substrate. Usually refers to a component that inserts a socket. The standard SIMM has 30 electrodes with a center distance of 2.54mm and two sizes of 72 electrodes with a center distance of 1.27mm. The 1 and 4 megabit DRAM SIMM with SOJ encapsulation has been widely applied in personal computers, workstations and other devices on printed substrates. At least 30 to 40% of DRAM are assembled in SIMM.

44.SIP (single in-line package)

Single row plug - in package. The pin is drawn from the side of the package and is arranged in a straight line. The package is side - shaped when assembled on the printed substrate. The pin center distance is usually 2.54mm, and the number of pins is from 2 to 23. Most of the pins are custom products. The shape of the package is different. Some packages that have the same shape as ZIP are also called SIP.

45.SKDIP (skinny dual in-line package)

A kind of DIP. The narrow body DIP with the width of 7.62mm and the center distance of the pin 2.54mm. It is usually called DIP (see DIP).

46. SHDIP(shrink dual in-line package)

SDIP. The name used by some semiconductor manufacturers.

47.SIL (single in-line)

SIP's alias (see SIP). SIL is the name of European semiconductor manufacturers.

48. QTP(quad tape carrier package)

The four side pins are loaded with load. The name used by the Japanese electronic machinery industry in April 1993 for the shape of the QTCP (see TCP).

49.QUIL (Quad in-line)

QUIP's alias (see QUIP).

50.QUIP (Quad in-line package)

The four line pin is inserted into the package. The pin is drawn from the two sides of the package, and each one is staggered down into four columns. The center distance of the pin is 1.27mm, and when the printed substrate is inserted, the center distance into the center becomes 2.5mm. So it can be used for standard printed circuit boards. A package that is smaller than the standard DIP. The Nec Corp adopted some kinds of packaging in the microcomputer chips of desktop and household appliances. There are two kinds of materials, ceramics and plastics. The pin number is 64.

51.SDIP (shrink dual in-line package)

Contractile type DIP. One of the intercalated packages has the same shape as DIP, but the pin center (1.778mm) is less than DIP (2.54 mm) so that the name is called. The number of pins is from 14 to 90. Also known as the SHDIP. There are two kinds of materials, ceramics and plastics.

52. QFP(FP)(QFP fine pitch)

integrate circuit packaging

The small center is QFP. The name stipulated in the standard of the Japanese Electronic Machinery Industry Association. The center distance of the pin is QFP of 0.55mm, 0.4mm, 0.3mm and so on, which is less than 0.65mm (see QFP).

53. QIC(Quad in-line ceramic package)

The other name for ceramic QFP. The names used by some semiconductor manufacturers (see QFP, Cerquad).

54.QIP(Quad in-line plastic package)

The other name for plastic QFP. The name used by some semiconductor manufacturers (see QFP).

55.QTCP(Quad tape carrier package)

The four side pins are loaded with load. One of the TCP packages is to form pins on the insulation belt and draw from the four sides of the package. It's a thin package that uses TAB Technology (see TAB, TCP).


IV.Development countermeasures and suggestions

  • Accurate product and market positioning

  • Abandoning the ideal model of production, learning and research

  • Innovative efficiency transcends traditional cost static efficiency

  • Overcoming accumulation and overcoming quick success and immediate interest

  • Promoting cooperation among enterprises and promoting industrial chain cooperation

  • Build the "new hometown" of the international elite and give full play to the advantages of the returnees

Book Recommendation

  • Integrated Circuits: How to Make Them Work (Practical Handbook)

Integrated circuits - or ICs - have largely replaced transistors in all forms of electronic equipment for the home and industry. The modern electronics engineer automatically adopts them as standard practice. This book offers a completely practical introduction for the amateur to the fascinating worlds of using ICs, in the home or workshop, and turning them into working circuits.This books will prove vital for anyone interested in, or in any way concerned with, modern electronics practice.

--RH Warring (Author)

  • Analysis And Design Of Analog Integrated Circuits, 5Th Ed, Isv

The fifth edition retains its completeness, updates the coverage of bipolar technologies, and enhances the discussion of bicmos. It provides a more unified treatment of digital and analog circuit design while strengthening the coverage of cmos. The chapter on non-linear analog circuits has been removed and chapter 11 has been updated to include an operational amplifier example. Models for integrated-circuit active devices bipolar, mos, and bicmos integrated-circuit technology single-transistor and multiple-transistor amplifiers current mirrors, active loads, and references output stages operational amplifiers with single-ended outputs frequency response of integrated circuits feedback frequency response and stability of feedback amplifiers nonlinear analog circuits noise in integrated circuits fully differential operational amplifiers

--Hurst,Gray, Lewis Meyer (Author)

  • Design of Analog CMOS Integrated Circuits

This textbook deals with the analysis and design of analog CMOS integrated circuits, emphasizing recent technological developments and design paradigms that students and practicing engineers need to master to succeed in today's industry. Based on the author's teaching and research experience in the past ten years, the text follows three general principles: (1) Motivate the reader by describing the significance and application of each idea with real-world problems; (2) Force the reader to look at concepts from an intuitive point of view, preparing him/her for more complex problems; (3) Complement the intuition by rigorous analysis, confirming the results obtained by the intuitive, yet rough approach.

--Behzad Razavi  (Author)

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