Home  Electronic Components and Parts Search

Jun 28 2018

How to Design a PCB Layout

Warm hint: The words in this article are about 1000 words and the reading time is about 5 minutes.

Article CorePCB Layout TutorialPurpose High-Quality PCB Design
English namePrinted Circuit Board CategorySelf-Contained Module 
FunctionMechanically support and electrically connect electronic componentsFeaturesCheaper and faster producing, but more difficult to repair and usually impractical

CatalogueⅠ MOSFET Processing(1) Standard VNPN2. GC-LCPNP
(1) Normal MOS transistor(2) Double-base VNPNⅤ Diode Processing
(2) Multi-finger MOSFET(3) LPNPⅦ Capacitor processing
(3) High-voltage transistor(4) LNPNⅧ Simplest Circuit—RS Flip Flop Identification
(4) Power-switching MOS transistorⅢ BICMOS processing(1) RS flip-flop using NAND gates
Ⅱ BJT Processing1. NPN transistors in the BICMOS processing(2) RS flip-flop using NOR gates


Ⅰ MOSFET Processing

(1) Normal MOS transistor

FIG.1_20180626155151.jpg

Layout of a digital MOS transistor and its equivalent circuit

The structure will be easily confused with polysilicon resistor, and the method of identification is:

  1. See whether the polysilicon resistor is placed above the active region.

  2. Find out how many output ports the polysilicon resistor has.

FIG.2_20180626155151.jpg

The aspect ratio of a MOS transistor

(2) Multi-finger MOSFET

FIG.3_20180626155151.jpg

Layout of a “stacked” wide transistor

The key to identifying the MOS transistor is to look at the polycrystalline silicon layer and check how many input ports it has.

(3) High-voltage transistor

FIG.4_20180626155151.jpg

Extended-drain, high-voltage transistor

FIG.5_20180626155151.jpg

Layout of a high-voltage transistor

The extended-drain, high-voltage transistor uses non-self-aligned processes and a n-well as the lightly doped drain.

FIG.6_20180626155151.jpg

Asymmetric source/drain MOS transistor

The specific high-voltage principle behind this asymmetric source/drain transistor structure is not yet very clear.

(4) Power-switching MOS transistor

FIG.7_20180626155151.jpg

Layout of a power-switching MOS transistor

Half of the area on the layout is used to make a key device in the circuit-power-switching MOS, and the layout is as above. The source and drain region is a matrix structure, and the drain electrode is also made in an n-well, which is an non-self-alignment process. Therefore, it is supposed that the transistor is a combination of waffle transistor and extended drain HV transistor, which can withstand high voltage and high current.

In addition, NMOS and PMOS in the layout can be identified by the following rules:

  1. In CMOS digital circuits, W/L of PMOS is large and that of NMOS is small.

  2. The source of PMOS is generally connected to a Vdd, and that of NMOS is generally connected to a Vss.

  3. Analog circuits do not fully obey the above rules, which can be analyzed in combination with the circuit structures. If the differential amplifier tail current is connected to Vss, then the MOS differential pair with tail current is supposed to be a NMOS, and the transistor load a PMOS.

What is a CMOS? [NMOS, PMOS]

Ⅱ BJT Processing

The basic rule: From the layout point of view, the collector and emitter of transistors have the same color. The BJT processing is generally divided into two kinds: VNPN and LPNPN, in which VNPN is divided into standard VNPN and double-base VNPN.

(1) Standard VNPN

FIG.8_20180626155151.jpg

 Standard VNPN

(2) Double-base VNPN

FIG.9_20180626155151.jpg

Double-base VNPN 

(3) LPNP

FIG.10_20180626155151.jpg

LPNP

FIG.11_20180626155151.jpg

LPNP

Other forms of layout:

FIG.12_20180626155151.jpg

(4) LNPN

FIG.13_20180626155151.jpg

LNPN

FIG.14_20180626155151.jpg

LNPN

This structure is generally different with VNPN because it uses N-SUB with P-WELL instead of P-SUB.

The distinction between NPN and PNP in layout can be made by following rules:

Except for very special cases, the collector of NPN is connected to the positive terminal and that of PNP is connected to the negative terminal of the power supply. The NPNs are small-size transistor and the PNPs are often large-size horizontal and vertical transistors.

Ⅲ BICMOS processing

1. NPN transistors in the BICMOS processing

FIG.15_20180626155151.jpg

NPN

Compared with the standard CMOS, a low concentration P region is added to form the base region in the N well, P+ to act as an active base, and N+ as an active emitter. And the deep N+ collector, the isolation groove...This is the double-well twin-buried-layer structure.

2. GC-LCPNP

FIG.16_20180626155151.jpg

GC-LCPNP

The traditional PNP emitter E is surrounded by poly gates to form a PMOS-like structure, and the circuit symbol is as shown in the diagram above.

The requirement of this added gate is vg > ve > Vb, and usually Vg should not be smaller than Ve. If it is smaller than ve, it will not work, so Vg>=Ve is what we emphasize here.

Assume that Vg is too small, then the voltage on the gate of PMOS  increases, causing the conduction of PMOS, which in turn makes Ve close to Vc (saturation).

The working principle of the PNP (similar to a common collector) can be analyzed by referring to the sectional view above (Ve >Vb>>Vc, the EB is forward biased, and the BC is reverse biased).

Hence we say that, this PMOS-like structure must be cut off.

However, it does not mean that E (emitter) is cut off. Instead, electrons are suppose to accumulate in B (base), which increases the electric field from E to B, and increases the concentration of the base. The electron passes through the base faster, arriving the emitter quickly.

The analyses lead to a conclusion that this structure improves the performance of PNP and it can work normally in the affected environment, which is also the reason why everyone is willing to adopt this structure now.

Ⅴ Diode Processing

Diodes are usually divided into normal diode and Zener diode. These two diode layouts can be identified by determining the MOS transistors and check how many output ports it has.

In addition, due to the need for circuit performance, there may be some relatively special diode layouts.

FIG.17_20180626155151.jpg

Special diode layout

Ⅵ Resistor processing

Resistor processing can be divided into three types: diff resistor, poly resistor and N-well resistor.

FIG.18_20180626155151.jpg

Three types of resistor

Ⅶ Capacitor processing

The most vivid capacitor structure is a dielectric layer sandwiched between two conducting plates. In layout designing, those can be used as conducting plates are Poly / METAL1 / METAL2 and the diffusion layer. There are several types of capacitors such as POLY-POLY, METAL-POLY, METAL2-METAL1, polysilicon-n+ diffusion MOS transistor and so on.

Here are some common capacitor layouts :

FIG.19_20180626155151.jpg

MMC

FIG.20_20180626155151.jpg

Sandwich

FIG.21_20180626155151.jpg

Sandwich

FIG.22_20180626155151.jpg

Sandwich

Ⅷ Simplest Circuit—RS Flip Flop Identification

(1) RS flip-flop using NAND gates

FIG.23_20180626155151.jpg

RS flip-flop using NAND gates

(2) RS flip-flop using NOR gates

FIG.24_20180626155151.jpg

RS flip-flop using NOR gates

Analysis of the two layouts revealed that the former basic unit is NAND and the latter basic unit is NOR. We can analyze the layout of these two circuits first, and then identify the RS flip-flop layout.

FIG.25_20180626155151.jpg

NMOS vs. PMOS

Notes: The very key is to check how many output ports connected to vdd and gnd.

FIG.26_20180626155151.jpg

Layout of the NAND and NOR gate


Book Recommendation

The EASY-PC Handbook: PCB Layout and Circuit Design by Computer

This book is a guide to the leading and readily available computer-aided design package, EASY-PC. Ian Sinclair explains clearly, using EASY-PC, how to get the best out of a PCB layout and design system. This book covers EASY-PC in detail, with step by step examples.

by Ian Sinclair

A Practical Guide to RF and Mixed Technology Printed Circuit Board Layout

Uccessful design of modern, complex mixed-technology printed circuit boards is an ever-evolving task. As technologies change, techniques employed by designers must evolve accordingly. The aim of this guideline is to ensure that designs are done as correctly as possible on the first attempt. Doing so has been repeatedly found to yield good results from simulations and testing, with minimal design modification required. 

by Brendon Parise


Relevant information about "How to Design a PCB Layout"

About the article "How to Design a PCB Layout", If you have better ideas, don't hesitate to  write your thoughts in the following comment area. You also can find more articles about electronic semiconductor through Google search engine, or refer to the following related articles:

Transistor Switching Circuit Design and Its Theory

LED Driver Basics and Its Circuit Design

Basic Introduction and Design flow of Programmable Logic Device FPGA

Design scheme of intelligent energy saving plugs based on AVR

0 comment

Leave a Reply

Your email address will not be published.

 
 
   
Rating: