Product Overview
Kynix Part #: | KY32-EP3SL50F484C4N |
Manufacturer Part#: | EP3SL50F484C4N |
Product Category: | Embedded - FPGAs (Field Programmable Gate Array) |
Stock: | Yes |
Manufacturer: | Altera |
Click Purchase button to buy original genuine EP3SL50F484C4N | |
Description: | IC FPGA 296 I/O 484FBGA |
Datasheet: | EP3SL50F484C4N Datasheet |
Package: | FBGA-484 |
Quantity: | 500 PCS |
EP3SL50F484C4N Images are for reference only.
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EP3SL50F484C4N Footprint
Product Attributes
Manufacturer: | Altera |
Product Category: | Embedded - FPGAs (Field Programmable Gate Array) |
Part Status: | Active |
Series: | StratixR III L |
Product: | Stratix III |
REACH Compliant: | Yes |
EU RoHS Compliant: | Yes |
Device Logic Cells: | 47500 |
Differential I/O Standards Supported: | LVPECL|LVDS |
Single-Ended I/O Standards Supported: | LVTTL|LVCMOS |
Device Number of DLLs/PLLs: | 4 |
External Memory Interface: | DDR2 SDRAM|DDR3 SDRAM|RLDRAM II|QDRII+SRAM |
Embedded-Block-RAM-EBR: | 297 kbit |
JESD-30 Code: | S-PBGA-B484 |
JESD-609 Code: | e1 |
Lead Finish(Plating): | SnAgCu |
Lead Shape: | Ball |
Mounting Type: | Surface Mount |
Mounting Style: | SMD/SMT |
Maximum Operating Temperature: | 85 °C |
Minimum Operating Temperature: | 0 °C |
Maximum Operating Supply Voltage: | 1.15 |
Minimum Operating Supply Voltage: | 0.86 V |
Maximum Number of User I/Os: | 296 |
Maximum Reflow Temperature: | 245 °C |
Reflow Solder Time (Sec): | 30 |
Number of Reflow Cycle: | 3 |
Number of I/Os: | 296 |
Number of I/O Banks: | 24 |
Number of Inputs: | 296 |
Number of Outputs: | 296 |
Number of Logic Blocks (LABs): | 1900 |
Number of Logic Elements/Cells: | 47500 |
Number of Multipliers: | 216 (18x18) |
Number of Global Clocks: | 16 |
Package-Case: | 484-BBGA, FCBGA |
Mfr Package Description: | LEAD FREE, FBGA-484 |
Package Body Material: | PLASTIC/EPOXY |
Package Code: | BGA |
Package Equivalence Code: | BGA484,22X22,40 |
Package Shape: | SQUARE |
Package Style: | GRID ARRAY |
Peak Reflow Temperature: | 245 °C |
Package Length: | 23 mm |
Package Width: | 23 mm |
Package Height: | 2.55 mm |
Seated Plane Height: | 3.05 mm |
Pin Pitch: | 1 mm |
Pin Count: | 484 |
PCB: | 484 |
Process Technology: | 65 nm |
Program Memory Type: | SRAM |
Shift Registers: | Utilize Memory |
Speed Grade: | 4 |
Sub Category: | Field Programmable Gate Arrays |
Supplier-Device-Package: | 484-FBGA (23x23) |
Supplier Cage Code: | 4BA62 |
Supported IP Core Manufacture: | Barco Silex/Mobiveil, Inc |
Technology: | CMOS |
Terminal Finish: | Tin/Silver/Copper (Sn/Ag/Cu) |
Terminal Form: | BALL |
Terminal Position: | BOTTOM |
Total Memory: | 2133 kbit |
Total-RAM-Bits: | 2184192 |
Total Number of Block RAM: | 6+108+950 |
Additional Feature: | IT CAN ALSO OPERATE FROM 1.05 TO 1.15V SUPPLY |
Descriptions
The Stratix® III family provides one of the most architecturally advanced, high-performance, low-power FPGAs in the marketplace.
Stratix III FPGAs lower power consumption through Altera’s innovative Programmable Power Technology, which provides the ability to turn on the performance where needed and turn down the power consumption for blocks not in use. Selectable Core Voltage and the latest in silicon process optimizations are also employed to deliver the industry’s lowest power, high-performance FPGAs.
Specifically designed for ease of use and rapid system integration, the Stratix III FPGA family offers two variants optimized to meet different application needs:
● The Stratix III L family provides balanced logic, memory, and multiplier ratios for mainstream applications.
● The Stratix III E family is memory- and multiplier-rich for data-centric applications.
Modular I/O banks with a common bank structure for vertical migration lend efficiency and flexibility to the high-speed I/O. Package and die enhancements with dynamic on-chip termination, output delay, and current strength control provide best-in-class signal integrity.
Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III family is a programmable alternative to custom ASICs and programmable processors for high-performance logic, digital signal processing (DSP), and embedded designs.
Stratix III devices include optional configuration bit stream security through volatile or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where ultra-high reliability is required, Stratix III devices include automatic error detection circuitry to detect data corruption by soft errors in the configuration random-access memory (CRAM) and user memory cells.
Product Features
v 48,000 to 338,000 equivalent logic elements (LEs) (refer to Table 1–1)
v 2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers
v High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18, and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
v I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for robust signal integrity
v Programmable Power Technology, which minimizes power while maximizing device performance
v Selectable Core Voltage, available in low-voltage devices (L ordering code suffix), enables selection of lowest power or highest performance operation
v Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per device
v Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration, clock switchover, programmable bandwidth, clock synthesis, and dynamic phase shifting
v Memory interface support with dedicated DQS logic on all I/O banks
v Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks
v Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide range of industry I/O standards
v Dynamic On-Chip Termination (OCT) with auto calibration support on all I/O banks
v High-speed differential I/O support with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry for 1.6 Gbps performance
v Support for high-speed networking and communications bus standards including SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI
v The only high-density, high-performance FPGA with support for 256-bit AES volatile and non-volatile security key to protect designs
v Robust on-chip hot socketing and power sequencing support
v Integrated cyclical redundancy check (CRC) for configuration memory error detection with critical error determination for high availability systems support
v Built-in error correction coding (ECC) circuitry to detect and correct data errors in M144K TriMatrix memory blocks
v Nios® II embedded processor support
v Support for multiple intellectual property megafunctions from Altera® MegaCore® functions and Altera Megafunction Partners Program (AMPPSM)
Product Functions
There is no relevant information available for this part yet.
Application
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Advantages and Disadvantages
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ECCN / UNSPSC
Description | Value |
ECCN: | 3A991.d.1 |
CAHTS: | 8542390029 |
CNHTS: | 8542319000 |
MXHTS: | 85423901 |
USHTS: | 8542390001 |
JPHTS: | 8542390990 |
TARIC: | 8542399000 |
Environmental & Export Classifications
Moisture Sensitivity Level (MSL) | 3(168 Hours) |
Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
Product Compliance
There is no relevant information available for this part yet.
Documents & Media
Product Manufacturer
Altera Corporation is an American manufacturer of programmable logic devices (PLDs), reconfigurable complex digital circuits.[1] Altera released its first PLD in 1984. Altera's main products are the Stratix, Arria and Cyclone series FPGAs, the MAX series CPLDs, Quartus II design software, and Enpirion PowerSoC DC-DC power solutions.
Altera and Intel announced on June 1, 2015 that they have agreed that Intel would acquire Altera in an all-cash transaction valued at approximately $16.7 billion. As of December 28, 2015, the acquisition had been completed.
Product Range
FPGAs | SoC FPGAs | PowerSoC |
ASICs | IP cores | Design software |
Distributors
Distributor | Stock | Manufacturer | Descriptions |
Kynix | 500 | Altera | IC FPGA 296 I/O 484FBGA |
Digikey | 0 | Intel | IC FPGA 296 I/O 484FBGA |
Mouser | 0 | Intel / Altera | FPGA - Field Programmable Gate Array FPGA - Stratix III 1900 LABs 296 IOs |
Alternative Models
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EP3SL50F484C4N Popularity by Region
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