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Mar 26 2019

MCIMX503EVM8B Datasheets| Freescale Semiconductor - NXP| PDF| Price| In Stock

Product Overview

Kynix Part #:

KY32-MCIMX503EVM8B

Manufacturer Part#:

MCIMX503EVM8B

Product Category:

Embedded - Microprocessors

Stock:

Yes

Manufacturer:

Freescale Semiconductor - NXP

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Description:

IC MPU I.MX50 800MHZ 400MAPBGA

Detailed Description:

ARM® Cortex®-A8 Microprocessor IC i.MX50 1 Core, 32-Bit 800MHz 400-MAPBGA (17x17)

Datasheet:

MCIMX503EVM8B Datasheet

Package:

400-LFBGA

Quantity:

77 PCS


MCIMX503EVM8B Images are for reference only.

MCIMX503EVM8B


CAD Models

Footprint

Footprint


Product Attributes

Manufacturer:

Freescale Semiconductor - NXP

Product Category:

Embedded - Microprocessors

Series:

i.MX50

Packaging:

Tray

Unit-Weight:

0.029584 oz

Mounting-Style:

SMD/SMT

Tradename:

i.MX

Package-Case:

400-LFBGA

Operating-Temperature:

-20°C ~ 70°C (TA)

Supplier-Device-Package:

400-MAPBGA (17x17)

Memory-Type:

L1/L2 Cache ROM SRAM

Voltage-I-O:

1.2V, 1.875V, 2.775V, 3.0V

Speed:

800MHz

Core-Processor:

ARMR CortexR-A8

Number-of-Cores-Bus-Width:

1 Core, 32-Bit

Co-Processors-DSP:

Multimedia; NEON? SIMD

RAM-Controllers:

LPDDR, LPDDR2, DDR2

Graphics-Acceleration:

Yes

Display-&-Interface-Controllers:

LCD

Ethernet:

10/100 Mbps (1)

SATA:

---

USB:

USB 2.0 + PHY (2)

Security-Features:

Boot Security, Cryptography, Secure JTAG

Number-of-Cores:

1 Core

Maximum-Operating-Temperature:

+ 70 C

Minimum-Operating-Temperature:

- 20 C

Operating-Supply-Voltage:

1.05 V

Application:

Multimedia Applications

Interface-Type:

1-Wire Ethernet I2C SPI UART USB

Core:

ARM Cortex A8

Processor-Series:

i.MX50

Data-Bus-Width:

32 bit

Package-Case:

MAPBGA-400

Maximum-Clock-Frequency:

800 MHz

L1-Cache-Instruction-Memory:

32 kB

L1-Cache-Data-Memory:

32 kB

Data-RAM-Size:

128 kB

Data-ROM-Size:

96 kB

I-O-Voltage:

1.05 V 1.225 V

L2-Cache-Instruction-Data-Memory:

256 kB

Number-of-Timers-Counters:

1 x 32 bit

Watchdog-Timers:

Watchdog Timer

Unit Weight:

0.029584 oz

Part Life Cycle Code:

Obsolete

Package Description:

LFBGA,

HTS Code:

8542.31.00.01

Risk Rank:

5.78

JESD-30 Code:

S-PBGA-B400

Length:

17 mm

Number of Terminals:

400

Package Body Material:

PLASTIC/EPOXY


Product Features

The i.MX50 applications processor is based on the ARM Cortex-A8 platform and has the following features:

• MMU, L1 instruction cache, and L1 data cache

• Unified L2 cache

• 800 MHz or 1 GHz target frequency of the core (including NEON, VFPv3, and L1 cache)

• NEON coprocessor (SIMD Media Processing Architecture) and Vector Floating Point (VFP-Lite) coprocessor supporting VFPv3

The memory system consists of the following components:

• Level 1 cache:

— Instruction (32 Kbyte)

— Data (32 Kbyte)

• Level 2 cache:

— Unified instruction and data (256 Kbyte)

• Level 2 (internal) memory:

— Boot ROM, including HAB (96 Kbyte)

— Internal multimedia/shared, fast access RAM (128 Kbyte)

• External memory interfaces:

— 16/32-bit DDR2-533, LPDDR2-533, or LPDDR1-400 up to a total of 2 GByte

— 8-bit NAND SLC/MLC Flash with up to 100 MHz synchronous clock rate and up to 32-bit hardware ECC for 1 Kbyte block size

— 16/32-bit NOR Flash with a dedicated 16-bit muxed-mode interface. I/O muxing logic selects EIMv2 port as primary muxing at system boot.

— 16-bit PSRAM, Cellular RAM

— Managed NAND, including eMMC up to rev 4.4

The i.MX50 introduces a next generation system bus fabric architecture that aggregates various sub-system buses and masters for access to system peripherals and memories. The various bus-systems and components are as follows:

• 64-bit AXI Fabric (266 MHz)—This bus-fabric is the SoC’s central bus aggregation point.

— Provides access to all slave targets in the SoC:

– ROM (ROMCP)

– On-chip RAM (OCRAM)

– External DRAM (DRAM MC)

– External static RAM (EIM)

– Interrupt controller (TZIC)

– Decode into the AHB MAX crossbar second level AHB fabric.

— Provides arbitration to the following masters in the system:

– ARM CPU complex

– Pixel processing pipeline (ePXP)

– Electrophoretic display controller (EPDC)

– eLCDIF LCD display controller

– DCP Crypto engine – BCH ECC engine

– MAX AHB crossbar

– GPU 2D

– SDMA

– USBOH1 (USB OTG and host controller complex)

– FEC Ethernet controller

• MAX AHB crossbar (133 MHz)—This connects the various AHB bus sub-segments in the system and provides decode into the following slaves:

— IP-Bus 1 (66 MHz)—This bus segment contains peripherals accessible by the ARM core and without DMA capability

— IP-Bus 2 (66 MHz)—This bus segment contains peripherals accessible by the ARM core and without DMA capability

 — APBH DMA bridge (133 MHz)—The APBH DMA bridge is a master to the MAX for its memory-side DMA operations. The APBH bus is an AMBA APB slave bus providing peripheral access to many of the high-speed IP blocks on the i.MX50.

• IP-Bus 3 (66 MHz)

—This third peripheral bus segment contains peripherals accessible by the ARM core and SDMA and as such houses peripherals with DMA capability. The IP-Bus 3 can be accessed by the ARM CPU through IP-Bus 1 and SPBA. • Quality of service controller (QoSC)

—This provides both soft and dynamic arbitration/priority control. The QoSC works in conjunction with the critical display modules such as the eLCDIF and EPDC to provide dynamic priority control, based on real-time metrics.

The i.MX50 makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia performance. The use of hardware accelerators provides both high performance and low power consumption, while freeing up the CPU core for other tasks.

The i.MX50 incorporates the following hardware accelerators:

• GPU2Dv1—2D Graphics accelerator, OpenVG 1.1, 200 Mpix/s performance

• ePXP—enhanced PiXel Processing Pipeline off loading key pixel processing operations required to support both LCD and EPD display applications


Product Functions

The i.MX50 applications processors are multimedia-focused products offering high-performance processing optimized for lowest power consumption. The i.MX50 processors are Freescale Energy Efficiency Solutions products. The i.MX50 is optimized for portable multimedia applications and features Freescale’s advanced implementation of the ARM Cortex-A8® core, which operates at speeds as high as 1 GHz. The i.MX50 provides a powerful display architecture, including a 2D Graphics Processing Unit (GPU) and Pixel Processing Pipeline (ePXP). Additionally, the i.MX50 includes a complete integration of the electrophoretic display function. The i.MX50 supports DDR2, LPDDR2, and LPDDR1 DRAM at clock rate up to 266 MHz to enable a range of performance and power trade-offs. The flexibility of the i.MX50 architecture allows it to be used in a variety of applications. As the heart of the application chipset, the i.MX50 provides a rich set of interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, and displays.


Application

• Displays:

— EPDC (i.MX508 Only)—Supporting direct-driver TFT backplanes beyond 2048 × 1536 at 106 Hz refresh (or 4096 × 4096 at 20 Hz)

— eLCDIF—Supporting beyond SXGA + (1400 × 1050) at 60 Hz resolutions with up to a 32-bit display interface

— On the i.MX508, both displays can be active simultaneously. If both displays are active, the eLCDIF only provides a 16-bit interface due to pin muxing.

• Expansion cards:

— Four SD/MMC card

• USB:

— One High Speed (HS) USB 2.0 OTG-capable port with integrated HS USB PHY

— One High Speed (HS) USB 2.0 host port with integrated HS USB PHY

• Miscellaneous interfaces:

— One-wire (OWIRE) port

— Two I2S/SSI/AC97 ports, supporting up to 1.4 Mbps each connected to the Audio Multiplexer (AUDMUX) providing four external ports

— Five UART RS232 ports, up to 4.0 Mbps each

— Two eCSPI (Enhanced CSPI) ports, up to 66 Mbps each plus CSPI port, up to 16.6 Mbps

— Three I2C ports, supporting 400 kbps

— Fast Ethernet controller IEEE 802.3, 10/100 Mbps

— Key pad port (KPP)

— Two pulse width modulators (PWM)

— GPIO with interrupt capabilities

— Secure JTAG controller (SJC)


Advantages and Disadvantages

There is no relevant information available for this part yet.


Product Compliance

USHTS:

8542310001

CAHTS:

8542310000

CNHTS:

8542319000

KRHTS:

8542311000

MXHTS:

85423102

TARIC:

8542319000


ECCN / UNSPSC

There is no relevant information available for this part yet.


Environmental & Export Classifications

Moisture Sensitivity Level (MSL)

3(168 Hours)

Lead Free Status / RoHS Status

Lead free / RoHS Compliant


Documents & Media

Datasheet

MCIMX503EVM8B Datasheet

iMS50 Family Fact Sheet

PCN

I.MX50 Datasheet Update

UPDATES FOR I.MX50 DATASHEET REV.4

PCN Design/Specification

I.MX50 Datasheet Revision 9/Aug/2013

I.MX50 Datasheet Revision 15/Oct/2013

I.MX50 Errata Update 02/Apr/2014


Product Manufacturer

NXP said it was the fifth-largest non-memory semiconductor supplier in 2016, and the leading semiconductor supplier for the secure identification, automotive and digital networking industries. The company was founded in 1953 as part of the electrical and electronics firm Philips, with manufacturing and development in Nijmegen, Netherlands. Known then as Philips Semiconductors, the company was sold to a consortium of private equity investors in 2006, at which point the company's name was changed to NXP.


Product Range

ARM ® PROCESSORS

AUTOMOTIVE PRODUCTS

IDENTIFICATION & SECURITY

Kinetis Cortex®-M Microcontrollers

In-Vehicle Network

MIFARE

LPC Cortex-M Microcontrollers

Microcontrollers and Processors

NFC


Distributors

Distributor

Stock

Manufacturer

Descriptions

Kynix

77 PCS

Freescale Semiconductor - NXP

IC MPU I.MX50 800MHZ 400MAPBGA

Digikey

Not Available

NXP USA Inc.

IC MPU I.MX50 800MHZ 400MAPBGA

Mouser

Not Available

NXP / Freescale

Processors - Application Specialised Codex Rev 1.1


Alternative Models

There is no relevant information available for this part yet.


Popularity by Region

There is no relevant information available for this part yet.


Market Price Analysis

There is no relevant information available for this part yet.


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