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Mar 15 2019

EP1S30F780C8N Datasheets| INTEL| PDF| Price| In Stock

Product Overview

Kynix Part #:

KY32-EP1S30F780C8N

Manufacturer Part#:

EP1S30F780C8N

Product Category:

Embedded - FPGAs (Field Programmable Gate Array)

Stock:

Yes

Manufacturer:

ALTERA

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Description:

IC FPGA 597 I/O 780FBGA

Datasheet:

EP1S30F780C8N Datasheet

Package:

BGA

Quantity:

806 PCS


EP1S30F780C8N Images are for reference only.

EP1S30F780C8N


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Product Attributes

Manufacturer:

ALTERA

Product Category:

Embedded - FPGAs (Field Programmable Gate Array)

Series:

StratixR

Product:

Stratix

Packaging:

Tray

Mounting-Style:

SMD/SMT

Tradename:

Stratix

Package-Case:

780-BBGA, FCBGA

Operating-Temperature:

0°C ~ 85°C (TJ)

Mounting-Type:

Surface Mount

Voltage-Supply:

1.425 V ~ 1.575 V

Supplier-Device-Package:

780-FBGA (29x29)

Number-of-Gates:

--

Number-of-I-O:

597

Number-of-LABs-CLBs:

3247

Number-of-Logic-Elements-Cells:

32470

Total-RAM-Bits:

3317184

Maximum-Operating-Temperature:

+ 70 C

Minimum-Operating-Temperature:

0 C

Operating-Supply-Voltage:

1.5 V

Operating-Supply-Current:

114 mA

Maximum-Operating-Frequency:

66 MHz

Package-Case:

FBGA-780

Number-of-I-Os:

597 I/O

Number-of-Logic-Array-Blocks-LABs:

3247

Number-of-Logic-Elements:

32470

Total-Memory:

3317184 bit

Rohs Code:

Yes

Part Life Cycle Code:

Obsolete

Package Description:

HBGA, BGA780,28X28,40

ECCN Code:

3A001.A.7.A

HTS Code:

8542.39.00.01

Risk Rank:

7.16

JESD-30 Code:

S-PBGA-B780

JESD-609 Code:

e1

Length:

29 mm

Moisture Sensitivity Level:

3

Number of CLBs:

3819

Number of Inputs:

726

Number of Logic Cells:

32470

Number of Outputs:

726

Number of Terminals:

780

Organization:

3819 CLBS

Package Body Material:

PLASTIC/EPOXY

Package Code:

HBGA

Package Equivalence Code:

BGA780,28X28,40

Package Shape:

SQUARE

Package Style:

GRID ARRAY, HEAT SINK/SLUG

Peak Reflow Temperature (Cel):

245

Programmable Logic Type:

FIELD PROGRAMMABLE GATE ARRAY

Qualification Status:

Not Qualified

Seated Height-Max:

3.5 mm

Subcategory:

Field Programmable Gate Arrays

Technology:

CMOS

Temperature Grade:

OTHER

Terminal Finish:

TIN SILVER COPPER

Terminal Form:

BALL

Terminal Pitch:

1 mm

Terminal Position:

BOTTOM

Time@Peak Reflow Temperature-Max (s):

40

Width:

29 mm

TARIC:

8542399000

Reprogrammability Support:

No

Opr. Frequency (MHz):

357.14

Number of Pins:

780


Features

■ 10,570 to 79,040 LEs; see Table 1–1

■ Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources

■ TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffersHigh-speed DSP blocks provide dedicated implementation of multipliers (fasterthan 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters

■ Up to 16 global clocks with 22 clocking resources per device region

■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover,

real-time PLL reconfiguration, and advanced multiplication and phase shifting

■ Support for numerous single-ended and differential I/O standards

■ High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second (Mbps)

■ Support for high-speed networking and communications bus standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4

■ Differential on-chip termination support for LVDS

■ Support for high-speed external memory, including zero bus turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM, double data rate (DDR) SDRAM,  DDR fast cycle RAM (FCRAM), and single data rate (SDR) SDRAM

■ Support for 66-MHz PCI (64 and 32 bit) in -6 and faster speed-grade devices, support for 33-MHz PCI (64 and 32 bit) in -8 and faster speed-grade devices

■ Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices

■ Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices

■ Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices

■ Support for multiple intellectual property megafunctions from Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions

■ Support for remote configuration updates


Advantages and Disadvantages

There is no relevant information available for this part yet.


Applications

The Stratix® family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities of up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. Stratix devices offer up to 22 digital signal processing (DSP) blocks with up to 176 (9-bit × 9-bit) embedded multipliers, optimized for DSP applications that enable efficient implementation of high-performance filters and multipliers. Stratix devices support various I/O standards and also offer a complete clock management solution with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs).


ECCN / UNSPSC

There is no relevant information available for this part yet.


Environmental & Export Classifications

Moisture Sensitivity Level (MSL)

3(168 Hours)

Lead Free Status / RoHS Status

Lead free / RoHS Compliant


Documents & Media

 

Datasheet

EP1S30F780C8N Datasheet

Stratix Device Datasheet

Stratix Device Handbook

780-FBGA Pkg Info

Virtual JTAG Megafuntion User Guide

PCN Obsolescence/ EOL

Mult Device EOL 1/Jun/2017

PCN Design/Specification

Package Height 03/March/2008

PCN Packaging

All Dev Pkg Chg 1/Aug/2018


Product Manufacturer

Altera Corporation is an American manufacturer of programmable logic devices (PLDs), reconfigurable complex digital circuits. Altera released its first PLD in 1984. Altera's main products are the Stratix, Arria and Cyclone series FPGAs, the MAX series CPLDs, Quartus II design software, and Enpirion PowerSoC DC-DC power solutions. Altera and Intel announced on June 1, 2015 that they have agreed that Intel would acquire Altera in an all-cash transaction valued at approximately $16.7 billion. As of December 28, 2015, the acquisition had been completed.


Product Range

FPGAs

ASICs

Processors

SoC FPGAs

IP cores

Boards & Kits

PowerSoC

Design software

Wireless


Distributors

Distributor

Stock

Manufacturer

Descriptions

Kynix

806 PCS

Altera

IC FPGA 597 I/O 780FBGA

Mouser

17

Intel / Altera

FPGA - Field Programmable Gate Array FPGA - Stratix I 3247 LABs 597 IOs

Octopart

--

Intel / Altera

FPGA Stratix® Family 32470 Cells 357.14MHz 0.13um (CMOS) Technology 1.5V 780-Pin FC-FBGA


Product Functions

Stratix® devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks. The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or

single-port memory up to 18-bits wide at up to 318 MHz. M512 blocks are grouped into columns across the device in between certain LABs. M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 291 MHz. These blocks are grouped into columns across the device in between certain LABs. M-RAM blocks are true dual-port memory blocks with 512K bits plus parity (589,824 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 144-bits wide at up to 269 MHz. Several M-RAM blocks are located individually or in pairs within the device’s logic array. Digital signal processing (DSP) blocks can implement up to either eight full-precision 9 × 9-bit multipliers, four full-precision 18 × 18-bit multipliers, or one full-precision 36 × 36-bit multiplier with add or subtract features. These blocks also contain 18-bit input shift registers for digital signal processing applications, including FIR and infinite impulse response (IIR) filters. DSP blocks are grouped into two columns in each device. Each Stratix device I/O pin is fed by an I/O element (IOE) located at the end of LAB rows and columns around the periphery of the device. I/O pins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and six registers for registering input, output, and output-enable signals. When used with dedicated clocks, these registers provide exceptional performance and interface support with external memory devices such as DDR SDRAM, FCRAM, ZBT, and QDR SRAM devices. High-speed serial interface channels support transfers at up to 840 Mbps

using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards.


Alternative Models

There is no relevant information available for this part yet.


Popularity by Region

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Market Price Analysis

Market Price Analysis


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