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Feb 20 2019

How to Rely on the Layout of the PCB to Avoid the Noise Problem of the Switching Power Supply?

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"Noise problem" - this is the four words that every board designer will hear. In order to solve the noise problem, it often takes several hours to carry out laboratory tests in order to find out the culprit, but in the end, it is found that the noise is caused by improper layout of the switching power supply. Solving such problems may require designing new layouts, resulting in product delays and increased development costs. 

Switch mode power supplies: their problems & how to filter HF noise out ?

This article will provide guidance on the layout of printed circuit boards (PCBs) to help designers avoid such noise problems. As an example, the switching regulator layout uses the dual channel synchronous switching controller ADP1850. The first step is to determine the current path of the regulator. The current path then determines the position of the device in the low noise layout design.

Article Core



Introduce how to rely on the layout of the PCB to avoid the noise problem of the switching power supply.


Semiconductor industry.





ⅠPCB Layout Guide

Step 1: Determine the Current Path

Step 2: Layout Physical Planning

Step 3: Power Devices - MOSFETs and Capacitors (Input, Bypass, and Output)

Ⅱ Thermal Considerations and Ground Plane

Ⅲ Current Detection Path

Ⅳ Feedback and Current Limit Detection Path

Ⅴ Switch Node

Ⅵ Gate Driver Path

Ⅶ Conclusion

ⅠPCB Layout Guide

Step 1: Determine the Current Path

In a switching converter design, the high current path and the low current path are very close to each other. The alternating current (AC) path carries spikes and noise, the high direct current (DC) path produces a considerable voltage drop, and the low current path is often sensitive to noise. The key to proper PCB layout is to identify critical paths, then arrange the device and provide enough copper area to avoid high currents from damaging low currents. Poor performance is grounded bounce and noise injection into the IC and the rest of the system.

Figure 1 shows a synchronous buck regulator design that includes a switching controller and the following external power devices: high-side switches, low-side switches, inductors, input capacitors, output capacitors, and bypass capacitors. The arrows in Figure 1 indicate the flow of high switching currents. Care must be taken to place these power devices to avoid undesirable parasitic capacitance and inductance, resulting in excessive noise, overshoot, ringing, and ground bounce.

Figure 1. Typical Switching Regulator (Displaying AC and DC Current Paths)

Figure 1. Typical Switching Regulator (Displaying AC and DC Current Paths)

Switched current paths such as DH, DL, BST, and SW must be properly routed away from the controller to avoid excessive parasitic inductance. The high δI/δt AC switching pulse currents carried by these lines may reach more than 3 A and last for a few nanoseconds. The high current loop must be small to minimize output ringing and avoid picking up extra noise.

Low-value, low-amplitude signal paths, such as compensation and feedback devices, are sensitive to noise. These paths should be kept away from the switching nodes and power devices to avoid injecting interference noise.

Step 2: Layout Physical Planning

The PCB floor plan is very important, the current loop area must be minimized, and the power supply components must be arranged so that the current flows smoothly, avoiding sharp corners and narrow paths. This will help reduce parasitic capacitance and inductance, eliminating ground bounce.

Figure 2 shows the PCB layout of a dual output buck converter using the switch controller ADP1850. Note that the layout of the power device minimizes current loop area and parasitic inductance. The dashed line indicates the high current path. This physical planning technique can be used by both synchronous and asynchronous controllers. In asynchronous controller designs, Schottky diodes replace low-side switches.

Figure 2. PCB layout of a dual output buck converter with ADP1850 controller

Figure 2. PCB layout of a dual output buck converter with ADP1850 controller

Step 3: Power Devices - MOSFETs and Capacitors (Input, Bypass, and Output)

The current waveform at the top and bottom power switches is a pulse with a very high δI/δt. Therefore, the path connecting the switches should be as short as possible to minimize the noise picked up by the controller and the noise transmitted by the inductive loop. When using a pair of DPAK or SO-8 packaged FETs on one side of the PCB, it is best to rotate the two FETs in opposite directions so that the switch nodes are on one side of the pair of FETs and use the appropriate ceramic bypass capacitors to the high side. Leakage current is bypassed to the low side source. Be sure to place the bypass capacitor as close as possible to the MOSFET (see Figure 2) to minimize the inductance around the loop through the FET and capacitor.

The placement of the input bypass capacitor and the input bulk capacitor is critical to controlling ground bounce. The negative terminal connection of the output filter capacitor should be as close as possible to the source of the low-side MOSFET, which helps to reduce the loop inductance that causes ground bounce. Cb1 and Cb2 in Figure 2 are ceramic bypass capacitors. The recommended values for these capacitors range from 1 μF to 22 μF. For high current applications, a larger value of the filter capacitor should be connected in parallel, as shown by CIN in Figure 2.

 Thermal Considerations and Ground Plane

Under heavy load conditions, the equivalent series resistance (ESR) of power MOSFETs, inductors, and bulk capacitors generates a large amount of heat. For efficient heat dissipation, the example of Figure 2 places a large area of copper beneath these power devices.

The heat dissipation effect of the multilayer PCB is better than that of the 2-layer PCB. To improve heat dissipation and electrical conductivity, 2 ounces of copper should be used on a standard 1 ounce copper layer. It is also helpful to have multiple PGND layers connected together via vias. Figure 3 shows the PGND layer on the top, third, and fourth layers of a 4-layer PCB design.

Figure 3. Sectional view: Connecting the PGND plane for improved heat dissipation

Figure 3. Sectional view: Connecting the PGND plane for improved heat dissipation

This multi-ground layer approach isolates noise-sensitive signals. As shown in Figure 2, the negative terminals of the compensation device, soft-start capacitor, bias input bypass capacitor, and output feedback divider resistor are all connected to the AGND plane. Do not connect any high current or high δI/δt paths directly to the isolated AGND plane. AGND is a quiet ground plane where no large current flows.

The negative terminals of all power devices (such as low-side switches, bypass capacitors, input and output capacitors, etc.) are connected to the PGND plane, which carries high current.

The voltage drop across the GND plane can be quite large, affecting output accuracy. Connecting the AGND plane to the negative side of the output capacitor through a wide trace (see Figure 4) can significantly improve output accuracy and load regulation.

Figure 4. Connection of the AGND layer to the PGND plane

Figure 4. Connection of the AGND layer to the PGND plane

The AGND layer is extended to the output capacitor, and the AGND and PGND layers are connected to the via at the negative terminal of the output capacitor.

Figure 2 shows another technique for connecting the AGND and PGND layers. The AGND plane is connected to the PGND plane through vias near the negative terminal of the output bulk capacitor. Figure 3 shows a section at a location on the PCB. The AGND and PGND layers are connected by vias near the negative terminal of the output bulk capacitor.

 Current Detection Path

In order to avoid the interference caused by noise, the current detection path layout of the current mode switching regulator must be properly configured. Dual-channel applications are especially important to eliminate crosstalk between any channels.

The dual-channel buck controller, the ADP1850, uses the low-side MOSFET's on-resistance RDS(ON) as part of the control loop architecture. This architecture senses the current flowing through the low-side MOSFET between the SWx and PGNDx pins. Ground current noise in one channel may be coupled into adjacent channels. Therefore, be sure to keep the SWx and PGNDx traces as short as possible and place them close to the MOSFET to accurately sense the current. The connection to the SWx and PGNDx nodes must use Kelvin detection techniques, as shown in Figures 2 and 5. Note that the corresponding PGNDx trace is connected to the source of the low-side MOSFET. Do not connect the PGND layer to the PGNDx pin at will.

Figure 5. Grounding techniques for two channels

Figure 5. Grounding techniques for two channels

In contrast, for dual-channel voltage-mode controllers such as the ADP1829, the PGND1 and PGND2 pins are connected directly to the PGND plane through vias.

 Feedback and Current Limit Detection Path

The feedback (FB) and current limit (ILIM) pins are low signal level inputs, so they are sensitive to capacitive and inductive noise disturbances. FB and ILIM traces should avoid approaching high δI/δt traces. Be careful not to let the traces form a loop, resulting in an increase in poor inductance. Adding a small MLCC decoupling capacitor (such as 22 pF) between the ILIM and PGND pins helps to further filter the noise.

 Switch Node

In the switching regulator circuit, the switch (SW) node is the most noisy place because it carries large AC and DC voltage/current. This SW node requires a large area of copper to minimize the resistive pressure drop. Placing the MOSFET and inductor close to each other on the copper layer minimizes series resistance and inductance.

Applications that are more sensitive to electromagnetic interference, switching node noise, and ringing can use a small buffer. The buffer is formed by connecting resistors and capacitors in series (see RSNUB and CSNUB in Figure 6) between the SW node and the PGND plane to reduce ringing and electromagnetic interference at the SW node. Note that adding a buffer may result in a slight decrease in overall efficiency by 0.2% to 0.4%.

Figure 6. Buffer and Gate Resistor Resistance

Figure 6. Buffer and Gate Resistor Resistance

 Gate Driver Path

The gate drive traces (DH and DL) also handle high δI/δt, which tends to produce ringing and overshoot. These traces should be as short as possible. It is best to route directly and avoid using feedthrough holes. If vias must be used, two vias should be used for each trace to reduce peak current density and parasitic inductance.

Connecting a small resistor (approximately 2 Ω to 4 Ω) in series with the DH or DL pin slows down the gate drive, which also reduces gate noise and overshoot. In addition, a resistor can be connected between the BST and SW pins (see Figure 6). Retaining space with a 0 Ω gate resistor during layout improves flexibility for future evaluations. The increased gate resistance increases the gate charge rise and fall times, resulting in increased switching power loss of the MOSFET.


Understanding the current path, its sensitivity, and proper device placement is key to eliminating the noise of PCB layout design. All of ADI's power device evaluation boards use the above layout guidelines for optimal performance. The evaluation board files UG-204 and UG-205 detail the layout and routing associated with the ADP1850.

Note that all switching power supplies have the same components and similar current path sensitivity. Therefore, the guidelines described for the ADP1850 for current mode buck regulators are equally applicable to the placement and routing of voltage mode and/or boost switching regulators.

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