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Feb 14 2019

What Are the New Memory Technologies and What Problems Can They Solve?

Warm hints: This article contains about 5000 words and reading time is about 20 mins.

Introduction

The rapid development of information technology requires storage technology to provide faster, larger capacity, lower power consumption, smaller size, longer life and higher reliability. At present, the development of storage technology has not kept pace with the development of processors, and has become a bottleneck restricting the development of computing technology. Traditional semiconductor process technology has gradually approached the physical limit, and it is difficult to greatly improve the performance of the memory. If there is a breakthrough, it is necessary to find another way and find new principles and methods. At present, some new storage technologies and corresponding new memories that are being researched and developed for the new century bring a hope for future information storage technologies, some of which have been or are partially implemented in the laboratory. Work towards commercialization goals. For example: Associative Memory Technology and Memory CAM with Addressable Addressing, Intelligent Processing Technology and Smart Memory, Superconducting Technology and Josephson Junction RAM, Holographic Storage Technology and Holographic Memory, Single Electronic Storage Technology and Single Electronic Memory, Proton Preservation Information Technology And proton memory, hydrogen atom storage technology and hydrogen atomic memory, biocircuit technology and protein molecular memory, next-generation information storage technology and high-speed mass storage, building electric field technology and analog memory, optical storage technology and three-dimensional optical memory, nanowires New information storage, etc.

Article Core

New Memory Technologies

Purpose

Introduce what the new memory technologies are and what problems they can solve?

Application

Semiconductor Industry.

Catalog

Introduction


Ⅰ Overview


Ⅱ Embedded Memory Problems


Ⅲ Power Problems in Large Systems


Ⅳ Why New Memory Can Solve the Problem


 

Ⅴ New Memory Type

5.1 PCM,Phase Change Memory

5.2 FRAM or FeRAM,Ferroelectric RAM

5.3 MRAM,Magnetic RAM

5.4 RRAM or ReRAM,Resistive RAM

 

Ⅵ Comparison of New Memory Technologies

6.1 Selector Type

6.2 Persistence

6.3 Scalability

6.4 Process Complexity

6.5 Disadvantages

Ⅶ Conclusion



 Overview

Small memory cell size, high performance, and low power consumption have always been the goal of the memory industry. However, below 14nm, the semiconductor process migrated to Fin-FET, a new transistor structure that could not be directly applied to existing embedded memory components. Furthermore, in order to meet the high computing power requirements of future artificial intelligence and edge computing, high-capacity memories such as DRAM and NAND flash memory have been unable to keep up with the demand.

Therefore, the semiconductor industry is at a turning point. Embedded memory in microcontrollers and ASICs, as well as discrete memory chips for all applications, from handheld mobile devices to supercomputers, are considering replacement. These replacements will help system designers reduce power consumption, extend battery life in handheld mobile devices or reduce data center system cooling requirements, as well as improve system performance to meet future high-performance computing systems. In some cases, replacing traditional memory types can also reduce system cost by using more advanced process technologies or system designs.

Although some new memory technologies have been developed, in this highly competitive market, only a few can succeed. However, no matter which technology wins, these new non-volatile technology systems will certainly consume less power than existing embedded NOR flash and SRAM, or discrete DRAM and NAND flash systems.

Jason Pontin: Can technology solve our big problems?


Ⅱ Embedded Memory Problems

There are two issues, the size of the embedded memory and the power consumption.

Advanced logic processes have surpassed 14nm and migrated to Fin-FET structures, and embedded NOR flash memories used for on-chip storage over the past decade or more have lost the ability to keep up with these processes. This problem is known as the "scaling limit" of flash - no matter how much the rest of the CMOS on the chip can shrink, the flash can't keep up. New embedded memory technologies must be available to match these advanced process ASICs and MCUs.

Embedded NOR flash is not the only one affected by process evolution. Embedded SRAM also faces similar problems. As the process shrinks to tens of nanometers or less, the size of the SRAM memory cell cannot keep up. Unlike NOR flash, the problem with SRAM is that the size of its memory cells does not shrink in proportion to the process. When the process shrinks by 50%, it may only shrink by 25%.

This limits the development of embedded NORs and embedded SRAMs, and we need new storage unit technologies to continue to scale down in proportion to the process. Fortunately, these technologies have existed and have been in development for many years.

Another issue is the strong argument for moving to new memory technologies, which are that memory consumes too much power. IoT and mobile devices operate on battery power, and their memory must be carefully chosen because they consume most of the battery power and reduce battery life, while new embedded memory technologies can reduce power consumption in response to this demand.

The next-generation mobile architecture will introduce higher computing power requirements for artificial intelligence and edge computing, while requiring lower power consumption to meet consumer expectations and win in tough market competition. Of course these must be achieved at low cost, which is the challenge of existing memory technologies. Most of today's battery-powered mobile devices and MCUs used in a variety of other applications are fabricated in a CMOS process, and the CMOS process supports two memory technologies: NOR flash and SRAM. Although these techniques are easily embedded in CMOS logic processes, they typically consume more power than expected.

When larger memories are needed, designers often add external memory chips, such as SPI (Serial Peripheral interface) NOR flash, NAND flash, DRAM, or a combination of these. However, these external memories have a greater impact on power consumption.

The problems with the two existing memories forced designers to begin evaluating new memory technologies in an attempt to solve them completely.


Ⅲ Power Problems in Large Systems

At the other end of the Internet of Things, in the cloud, the data center server's memory and data storage architecture is also important because power consumption is often one of the most costly elements of the data center, especially when it comes to cooling systems.

DRAM and NAND flash are the mainstream storage technologies used today in computing systems, from smartphones to data processing devices. However, for the design of the computing system, these two memory types cannot exist alone, because although the DRAM supports fast reading and writing, the charge of the capacitor of the DRAM memory cell will decay and disappear within a few milliseconds, so it is necessary to constantly Refreshing, while refreshing consumes a lot of power. Even if the system is idle, DRAM needs to be constantly refreshed with power.

Approximately 20% of the power consumed by the 8Gb DRAM chip is used for refresh, accounting for 25 milliwatts of total chip power consumption of 140 milliwatts. If the power is turned off, the contents of the DRAM will disappear (volatile memory) - even if the power is restored, the DRAM is not suitable for use as a boot, application, operating system, etc. code storage. The system must be paired with other nonvolatiles. Sex memory to perform code storage functions.

In addition, DRAM is relatively slow due to its multIplexed addressing technology. DRAM row address selection (RAS) and column row address selection (CAS) allow random reads to take between 25 and 300 nanoseconds (ns), and this extended time results in higher total energy consumption.

Flash Memory stores data that is not attenuated and can retain its content for many years after a power outage, but NOR flash is much more expensive than DRAM, and NAND flash is sequential reads and cannot be accessed to specific bytes. This does not match the need for computer operations to randomly address reads. So NAND flash must be paired with DRAM for code storage use.

Like DRAM, NAND flash also has some features that cause it to consume more power than expected. First, it requires an on-chip charge pump to generate a high internal voltage. Second, the write speed of NAND flash is also very slow. The most troublesome thing is that the NAND flash can't directly overwrite the old data when writing. Before the new data is written to the flash, the original stored data must be erased, and the entire page must be written once (Page, usually 8,096 bytes), it is not possible to write only a single specific byte.

Flash technology does not use the same mechanism to program or erase content. You can't just erase a single bit, byte, or page. Instead, you must pick up the block. The block usually contains Hundreds of thousands of pages. Page writing is a slow and energy-intensive process that typically takes 300 microseconds (μs) and consumes 80 microjoules (compared to 2 microjoules when read). Block erase (requires the high internal voltage mentioned above) takes longer, typically 2 milliseconds (ms), and consumes 150 microjoules of energy. Despite these big drawbacks, NAND flash systems are very cheap, so designers are willing to sacrifice these NAND complex write processes and high energy costs in exchange for their low cost.

Most smartphones and computing systems use a mix of DRAM and NAND flash to meet their memory and storage needs. In smartphones, when the phone is turned on, DRAM saves a copy of the program for execution, while NAND stores programs, photos, videos, music, and other speed-insensitive data when the power is turned off. The compute system server stores programs and data in its DRAM main memory (the server does not power down unless there is a power outage), and an SSD solid state drive (NAND State Drive) using NAND flash is configured for long-term and backup storage.

Smaller systems may use NOR flash instead of NAND flash and SRAM instead of DRAM, provided their memory requirements are very small. The cost per byte of NOR flash is one or two orders of magnitude higher than NAND flash, and the cost of SRAM is orders of magnitude higher than the cost of DRAM.


Ⅳ Why New Memory Can Solve the Problem

The aforementioned power consumption of memory used today has not existed in many of the new memory technologies currently under development. In addition, these new types of memories are non-volatile, so there is no need to refresh them. This automatically reduces power consumption by 20% compared to DRAM. Since they both overwrite old data without erasing, you can save the high erase power required for flash and the delay caused by slow erase cycles (this property is called In-Situ Programming). Compared to flash memory, these new technologies have very low write process energy requirements that reduce or eliminate the need for inefficient charge pumps. Finally, all of these new technologies provide random data access, reducing the need to keep two copies—one in flash and one in DRAM.

Needless to say, whenever any new memory technology is used to replace today's traditional DRAM + NAND flash architecture, all of these attributes will result in significant power savings and performance improvements.

The new types of memory we will introduce include the following.

new types of memory

Most new memory technologies have the following attributes:

All of these are non-volatile or persistent, and have a distinct advantage over DRAMs that require periodic refresh and high power requirements.

They do not require the high charge pump erase/write voltage required for flash memory.

None of them use the clumsy block erase/page write method required for flash (NAND and NOR), which greatly reduces write power requirements while increasing write speed.

Some of these can be downsized by processes to reduce costs, surpassing today's deep-rooted memory technologies: DRAM and flash.

Selector Device

An important difference between many of these memory types is how they are addressed, which is done through the Bit Selector. Some selector components are Transistors, which limit the size of the memory cells to a small extent. Others use diodes or other double-ended selector components, which can reduce the size of the memory cells and help stack the memory bits into a 3D array. The type of selector affects the cost of these memories and may be the cause of the difficulty in producing these components.

The double-ended selector unit achieves the ideal 4f2 unit area, the “f” is the minimum feature size of the chip manufacturing process, and the 4f2 unit is the square of the double minimum feature size (4f2 = 2f x 2f). On the 14nm process (f = 14nm), the number is 2 x 14nm x 2 x 14nm or 4 x (14nm)2. The 4f2 memory cell area is the smallest cell area that all memories can currently manufacture. Transistor-based memory cells are typically 8f2, but in some cases can be scaled down to 6f2.

Memory cells using double-ended selectors have another advantage, that is, they can be stacked to further reduce cost. So far, no company has tried to stack memory cells using transistor selectors.

There are two types of double-ended selectors: simple diodes and bidirectional selectors. In both cases, the diode is easier to design.


Ⅴ New Memory Type

5.1 PCM,Phase Change Memory

Phase Change Memory, also known as PRAM, has been studied for decades, and Intel co-founder Gordon Moore published a paper describing early prototypes in 1970. The phase change memory converts the phase change material between a low resistance crystalline (conductive) state and a high resistance amorphous (non-conductive) state by thermal energy transition. Also for this reason, phase change memories are also classified in the resistive memory (RRAM) classification.

PCM,Phase Change Memory

Image Source: Intel & ObjecTIve Analysis (Modified by Author)

When the PRAM performs the Set and Reset functions, the current moves in the same direction, so a simple diode can be used as the selector device, which makes the PRAM easier to design and produce because the diode is more than a bidirectional selector. It's much simpler. Since the memory cells are built on top of CMOS logic and are designed for stacking, the diode selector must use new materials instead of building it in the underlying CMOS. This increases the number of layers in wafer production and relatively increases the cost of the chip.

Intel and Samsung produced the first commercial PCM chip in 2006. The Intel chip has been in production for many years, and the Samsung chip was only one year before it was discontinued. Highly anticipated, developed by Intel and Micron, called 3D XPoint (XPoint is pronounced "Crosspoint"), is also a phase change memory (although Intel denies that it is PRAM (or RRAM), but reverse engineer (Reverse Engineers) After analyzing its chip, it is said to be). 3D XPoint is designed to be the new memory layer between DRAM and NAND flash SSDs in computing systems.


5.2 FRAM or FeRAM,Ferroelectric RAM

Ferroelectric memories, called FRAM or FeRAM, were introduced around 1987, but were not commercialized until the mid-1990s. Although called ferroelectric memory, FRAM does not use ferroelectric materials. The name stems from the fact that the behavior of the bit storage mechanism is similar to the behavior of ferromagnetic storage, that is, hysteresis, which is the basis of magnetic recording. The voltage-current relationship of FRAM has a characteristic hysteresis loop that can be used to store bits. A positive current will cause the bit cell to be in a positive biased state when shifted, while a negative current will change the state of the bit cell to a negative bias. The iron potential unit is stored using a crystal with one atom in the center. The atom is at the top or bottom of the crystal. Bit storage is a function of the position of the atom.

FRAM or FeRAM,Ferroelectric RAM

Image Source: ObjecTIve Analysis (Modified by Author)

Both Ramtron and Symetrix dominate the development of FRAM, each using a different material. The technology used by Ramtron is based on a memory crystal formed by a material called lead zirconium-titanium (PZT). PZT is not popular in semiconductor factories because the high ion transport properties of lead can contaminate silicon wafers. Symetrix's proprietary materials, although more complex, have encountered similar problems. Therefore, new ferroelectric memory materials continue to be developed.

An unfortunate fact of FRAM is that its reads are destructive and must be offset by subsequent writes after each read to restore the contents of the bit to its original state. Not only is this time consuming, but it also doubles the power consumed by the read cycle, which is a potential problem for power sensitive applications. However, FRAM's unique low write power consumption is its selling point.

In 1990, Ramtron's partner Fujitsu used embedded FRAM for mass production of subway fare card chips. FRAM was chosen because of its unique low write energy, allowing the chip to power the data read and write via interrogating radio signals without any additional power.

Current FRAM memory cells are based on a two-transistor, dual-resistor unit (2T2R), resulting in at least twice the size of a DRAM bit cell. The 1T1R memory cell is under development and will only make FRAM cost close to the cost of DRAM after development.


5.3 MRAM,Magnetic RAM

Magnetic RAM or MRAM is a natural result of magnetic recording technology. In fact, MRAM was the core memory of the earliest computers, which was replaced by SRAM and then replaced by DRAM in the 1970s.

The most primitive MRAM is called “Toggle MRAM” or “SRAM Type MRAM”, which reads them by magnetizing and degaussing bit cells, forcing them into different states. The current required to do so is inherently controllable, but at about 75 nm process nodes, the current becomes uncontrollable because the current remains the same, but the conductor shrinks with the process, causing the current density to be unacceptably high. So the researchers started experimenting with new methods, starting with STT (Spin Torque Tunneling) and going to pSTT (Perpendicular Spin Torque Tunneling). The STT-MRAM that everyone is talking about now is PSTT-MRAM. MRAM technology also has a SOT (Rotary Orbital Tunnel), which uses a three-terminal MTJ structure to separate the read and write paths, so it has faster read and write speeds and lower power consumption than STT-MRAM, but It is still in the research and development stage.

All of these components use the "Giant Magnetoresistive Effect" of the Tunneling Layer to read the bit cells: when the magnetic directions on both sides of the layer are the same, the layer provides low resistance, so the current is large. However, when the magnetic directions are opposite, the resistance will become high, causing the current flow to be interrupted. The base unit requires three or more layers of stacking, two magnetic layers and one tunnel layer.

MRAM,Magnetic RAM

Image Source: Avalanche Technology (Modified by Author)

There are two types of STT MRAM, one is a smaller but slower single-transistor (1T) cell, and the other is a larger but faster two-transistor unit (2T). Single-Transistor STT MRAM Each cell requires a transistor and a Magnetic Tunnel Junction (MTJ) called 1T1R. It has a chip size comparable to DRAM, but its 200ns write cycle is relatively slow. For faster SRAM-like write speeds, designers use a cell with two transistors, called 2T2R, to support high-speed differential sensing. However, this will more than double the size of the MRAM chip, resulting in a significant increase in cost.

Due to the large area of the embedded SRAM, the embedded NOR flash cannot continue to follow the process shrink, and STT-MRAM is gaining more and more attention. Everspin is aligned with Global Foundries, UMC and Avalanche Technology are aligned to promote STT-MRAM. They have introduced 2x nm embedded STT-MRAM with Samsung and TSMC to replace embedded NOR flash.

IBM's just-released 19 TB SSD uses Everspin's STT-MARM instead of DRAM as the SSD's Write Cache, primarily focusing on its non-volatile nature. Because DRAM is volatile. Therefore, relying on Supercaps to supply power when the power is off, MRAM can eliminate these bulky supercapacitors, which is another step in the application of STT-MRAM.

STT-MRAM is optimistic that it can be easily extended to less than 10nm, and its scalability makes STT-MRAM an alternative to DRAM and flash memory for low-density and medium-density applications in the next few years.


5.4 RRAM or ReRAM,Resistive RAM

Resistive memory, called ReRAM or RRAM, includes many different technology categories, including Oxygen Vacancy Memories, Conductive Bridge Memories, Metal Ion Memories, Memristors, as well as Carbon Nano-tubes, some even believe that phase change memory should also be included in this category. Common to all of these techniques is that the memory mechanism consists of a resistor that is in a high resistance or low resistance state to indicate "1" or "0". Current flows through the resistor to read it and uses a higher current to cover it. Among them, oxygen vacancy ReRAM is also called Oxide-based ReRAM .

ReRAM promises to simplify and shrink memory cells because they do not necessarily use transistors as selectors, but instead use double-ended selectors built above or below the bit cells. This should not only lower the memory cell to its theoretical minimum size of 4f2, but also allow the memory cells to be stacked vertically, greatly increasing chip density and reducing cost.

ReRAM currently available for production includes Crossbar's 40nm ReRAM, Adesto's 130nm CBRAM and Panasonic's 130nm TaOx ReRAM. Crossbar and Panasonic's processes can already be embedded in semiconductor foundry CMOS logic processes, while Adesto is currently produced as discrete chips.

Crossbar's ReRAM sandwiches a metal oxide material between the two electrodes. The unprogrammed cell has nano-conductive metal filaments (nano-conductive metal filaments less than 5 nm wide are composed of ionic atoms). Will conduct current. By passing a higher current in the correct direction, nano-conductive metal filaments are formed, and the metal filaments are almost, but not completely, bridged between the two electrodes. When a small read current passes through the cell in the same direction, the last gap is bridged and the bit cell becomes fully conductive. A small reverse read current will cause the gap to be inconsistent, and a larger reverse current will completely clear the conductive path. Crossbar is currently working with SMIC to produce its 40nm ReRAM and has begun to develop 1x nm embedded designs.

RRAM or ReRAM,Resistive RAM

Image Source: Objective Analysis (Modified by Author)

The Crossbar's ReRAM unit is “self-selecting” because the selector itself is part of the unit, which makes the unit operate like a diode, so no selector components are needed. This greatly simplifies the production process because the cells are composed of a single combined selector component + bit cell, while other Re-RAM technologies require a selector component that is separate from the bit cell. This is the biggest advantage of Crossbar ReRAM.

Adesto's CBRAM (conductive bridge RAM) also creates a resistive state by constructing and destroying conductive filaments. The difference, however, is that CBRAM injects copper or silver metal into the silicon to form a conductive bridge on the chalcogenide glass insulator between the two electrodes. This conductive bridge is only a few atoms wide. A positive current moves silver ions from the anode of the cell into the glass insulator, forming a conductive path. A reverse current moves these silver ions back to the anode, breaking the conductive bridge and cutting off the current path.

RRAM or ReRAM,Resistive RAM

Image Source: Adesto Technologies (Modified by Author)

Panasonic has integrated oxygen-vacuum-based ReRAM into its 130 nm MCU product line and announced in 2017 that it will work with foundry UMC to develop the 40 nm process.

These memories are glass insulators that use high voltages to move atoms in or out of the bit cells to form or remove conductive paths. Another oxygen vacancy ReRAM technology was developed by HP called the Memristor. Although the company proved this to be a revolutionary change, unlike any previous technology, it was carefully examined that it was just another name for oxygen-vacant memory. Previous HP research has produced four-transistor cells (4T2R) and one transistor cell (1T1R), but the company has not released any new news recently.

Another interesting type of ReRAM is carbon nanotube (CNT, Carbon Nanotubes) memory. The memory uses a deposited film (or fiber) of carbon nanotubes in a silicon substrate to store the bits. When the current flows through the cell in one direction, the nanotubes are compressed into a highly conductive state. When the current is reversed, the nanotubes expand so that the conductivity is lowered. When the current is removed, the programmed bit cells remain in their compressed state. Nantero dominates the development of carbon nanotube memory, so this memory is also known as NRAM and has been licensed to Fujitsu as a possible successor to FRAM, but NRAM has not yet been sampled.

Image source : Nantero

Image source : Nantero


Ⅵ Comparison of New Memory Technologies

Table 1 compares the components reviewed in this white paper.

Perhaps the most important factor in this comparison is the size of the unit, because it determines the cost. Cost is very important in the memory technology selection process - more expensive technology is often replaced by low-cost technology, even if this change requires a large number of solutions.


6.1 Selector Type

The technique of using a transistor as a selector mechanism (represented as 1T1R or 2T2R in the table) will have a larger bit cell size than using a double-ended selector ("S" in "1S1R") or diode (1D1R). The 1TnR in the .Crossbar field means that the company's unit has a built-in selector element that behaves like an internal diode. Each cell group requires a transistor, but this only adds a small percentage of the effective size of the cell.

The creation of selectors increases the complexity of wafer processing, and the complexity increases the cost of wafer processing. But the impact is not the biggest. Unit size has a far-reaching impact on the cost of memory. The 8f2 unit consumes twice as much area as the 4f2 unit, and the FRAM 30f2 unit consumes 7.5 times the area of any 4f2 technology.

The cell size not only determines the cost of the memory, but also limits the maximum amount of memory that can be generated in a given area. Many embedded designs have limited chip area available for on-chip memory. Those memories with the smallest cell size support the largest storage density for a given amount of space.


6.2 Persistence

All of these technologies are non-volatile compared to the prior art and are a significant advantage not available in DRAM, and they all support In-Situ Programming, which makes them faster than NAND or NOR flash. 


6.3 Scalability

Another important consideration is the scalability of the technology. Some new memory technologies, especially FRAM and PCM, have faced challenges. However, FRAM has not been successfully scaled below 90nm. The PCM's “on” resistance will increase as the cell size shrinks, making the technology face a lot of noise when the process shrinks, although PCM researchers succeeded a decade ago. A 5nm unit has been developed.

Oxygen Vacancy ReRAM is said to have problems scaling to below 10nm. Adesto's conductive bridge technology and Crossbar's nano-conductive metal filament technology are expected to be below 10nm.


6.4 Process Complexity

PCM (Intel's 3D XPoint memory) and Crossbar's conductive metal filament memory have advantages in this regard because their selector components are simpler than other technologies. The Crossbar's selector is contained in the bit cell, and the PCM uses current for set, reset and read operations in the same direction, so it requires only a simple diode (diode). Of the two, the Crossbar unit's process is simpler, and because there are no selector components, it requires less deposited layers.


6.5 Disadvantages

All of these new memory technologies do have some drawbacks compared to today's robust memory technologies: no speed can be as fast as SRAM and DRAM. Moreover, in the next few years, no one can compete with NAND flash in terms of cost, mainly because of the size of the economy.

In embedded applications, we typically use NOR flash to store code and data, but embedded NOR flashes can't keep up with advanced processes that continue to shrink cell sizes, and these new technologies offer ways to go beyond embedded NOR extension limits. For applications that cannot use NOR flash and must use an alternative technology, the new technology is usually chosen based on the cost of adding to the chip. These applications will therefore tend to use techniques that provide the smallest cell size and the least increase in wafer processing costs.


Ⅶ Conclusion

Due to process limitations and power consumption considerations, the memory industry has entered an era in which alternative technologies must be evaluated and developed. For decades, researchers have been studying several new types of storage technologies that are competing for competition and hope to become a new memory technology that can replace embedded NOR flash and even DRAM.

This article highlights some of the new memory technologies and explores the limitations they face in scaling to state-of-the-art process nodes and maintaining compelling performance at affordable manufacturing costs. Memory companies and semiconductor foundries are working closely together to develop and extend embedded memory to mass production. With standard CMOS materials and simple manufacturing processes and tools, the chances of success in a highly competitive market will be greatest.

While this article provides some reasons why some technologies are more successful than others, the ultimate strategic synergy between adopters and memory IP providers and manufacturing partners will determine which technologies will become non-volatile memory. New choice.

New Memory Technologies

Table 1


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