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XC7VX415T-3FF1158E Datasheets| Xilinx Inc.| PDF| Price| In Stock

Author: Apogeeweb
Date: 2 Sep 2019
 1079
Embedded - FPGAs (Field Programmable Gate Array)

Product Overview

Kynix Part #:

KY32-XC7VX415T-3FF1158E

Manufacturer Part#:

XC7VX415T-3FF1158E

Product Category:

IC Chips

Stock:

Yes

Manufacturer:

Xilinx Inc.

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Description:

-

Datasheet:

XC7VX415T-3FF1158E Datasheet

Package:

BGA

Quantity:

88 PCS


XC7VX415T-3FF1158E Images are for reference only.

XC7VX415T-3FF1158E Image 


CAD Models

There is no relevant information available for this part yet.


Product Attributes

Categories

Integrated Circuits (ICs)

Embedded - FPGAs (Field Programmable Gate Array)

Manufacturer

Xilinx Inc.

Series

Virtex®-7 XT

Base Part Number

XC7VX415T

Package Description

FBGA-1156

REACH Compliant

Yes

Status

Active

Programmable Logic Type

FIELD PROGRAMMABLE GATE ARRAY

Clock Frequency-Max

1,818 MHz

Clock Management

MMCM, PLL

Data Rate

28.05 Gb/s

Distributed RAM

6,525 kbit

Embedded Block RAM - EBR

31,680 kbit

In System Programmability

Yes

JESD-30 Code

S-PBGA-B1156

Moisture Sensitivity Level

4

Maximum Number of User I/Os

350

Number of CLBs

32,200

Number of Inputs

350

Number of Logic Cells

412,160

Number of Logic Units

257,600

Number of Outputs  

350

Number of Terminals

1156

Number of I/O

350

Number of Logic Blocks (LABs)

32,200

Number of Registers

516,800

Operating Temperature

0°C ~ 100°C (TJ)

Organization

32,200 CLBS

Package Body Material

PLASTIC/EPOXY

Package Code

BGA

Packaging

Tray

Product Range

Virtex-7 XC7VX415T Series

Package Type

FCBGA

Package Equivalence Code

BGA, BGA1156,34X34,40

Product Dimensions

35 x 35 mm

Package Shape

SQUARE

Propagation Delay

0.09 ns

Product Type

FPGA - Field Programmable Gate Array

Package Style

GRID ARRAY

Peak Reflow Temperature (Cel)

NOT SPECIFIED

Power Supplies

1,1.8 V

Pin Count

1156

PCB

1156

Package / Case

1156-BBGA, FCBGA

Supplier Device Package

1157-FCBGA (35x35)

Qualification Status  

Not Qualified

RAM Bits

32,440,320 b

Rohs Code

No

Risk Rank

5.85

Radiation Hardening

No

Sub Category

Field Programmable Gate Arrays

Supply Voltage-Nom

1.0 V

Supply Voltage-Min

0.97 V

Supply Voltage-Max

1.03 V

Speed Grade

3

Surface Mount  

Yes

Technology

CMOS

Terminal Form

Ball

Terminal Pitch  

1.0 mm

Terminal Position

Bottom

Time@Peak Reflow Temperature-Max (s)

NOT SPECIFIED

Typical Operating Supply Voltage

1.0 V

Tradename

Virtex

Length

35 mm

Width

35 mm


Features

  • Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.

  • 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.

  • High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.

  • High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to maximum rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.

  • A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.

  • DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering.

  • Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.

  • Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.

  • Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.

  • Low-cost, wire-bond, lidless flip-chip, and high signal integrity flipchip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.

  • Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power.


Advantages and Disadvantages

Advantages 

Optimized for highest system performance and capacity with a 2X improvement in system performance. Highest capability devices enabled by stacked silicon interconnect (SSI) technology.

Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.


Applications

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Product Functions

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ECCN / UNSPSC

There is no relevant information available for this part yet.


Environmental & Export Classifications

Moisture Sensitivity Level (MSL)

4 (72 Hours)

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant


Documents & Media

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Product Manufacturer

Xilinx, Inc. is an American technology company and is primarily a supplier of programable logic devices. It is known for inventing the field-programming gate array and as the semicondcutot company that created the first fabless manufacturing model. Ross Freeman, Bernard Vonderschmitt, and James V Barnett II, former employees of Zilog, an integrated circuit and solid-state device manufacturer, co-founded Xilinx in 1984 with headquarters in San Jose, USA.


Product Range

Devices

Boards

Developer Tools

ACAPs

Accelerator Cards

Vivado Design Suite - HLx Editions

FPGAs & 3D ICs

Evaluation Boards

SDAccel Development Environment

SoCs, MPSoCs & RFSoCs

System-on-Modules (SoMs)

SDSoC Development Environment


Distributors

Distributor

Stock

Manufacturer

Descriptions

Kynix Semiconductor

88 PCS

Xilinx, Inc.

-

Digi-Key

0

Xilinx, Inc.

-

Avnet

Americas - 16

Xilinx, Inc.

-

Mouser

0

Xilinx, Inc.

FPGA - Field Programmable Gate Array


Alternative Models

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Popularity by Region

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Market Price Analysis

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